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I'm using the (probably incorrect!) command 

yosys -f verilog -p "prep; show stretch count.dot" count.v

for the following simple example

module count(input clk,output [7:0] LEDS);

reg [26:0] count;
assign LEDS = count[26:19];

always @(posedge clk) begin
    count <= count + 1;
end

endmodule

Its not working as I'd expect giving no output to a file name I don't want...

3. Generating Graphviz representation of design.
Writing dot description to `/home/chris/.yosys_show.dot'.
ERROR: Nothing there to show.

Whats the correct way to do this?

Chris Camacho
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1 Answers1

1

The command line your are apparently looking for is:

yosys -p "prep; show -stretch -prefix count -format dot" count.v
CliffordVienna
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