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Does anyone know a way to make Systemverilog print something I want one time at the elaboration phase?

I know you can use new $error() system call to print errors at the elaboration phase, but I just want to print info there (not an error) one time. Is it possible to do with $info() call, or is there another way?

Also, preferably the info would print before the errors.

user5888527
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1 Answers1

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module top;

$info("I could have tried this before posting");

endmodule
dave_59
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  • I did try that its not working. Is it because info is inside an initial block? – user5888527 Mar 11 '16 at 15:10
  • DUPLICATE POST SORRY – user5888527 Mar 11 '16 at 15:11
  • Maybe your tool/version does not support it. It works for me in ModelSim/Questa. I have no initial block. – dave_59 Mar 11 '16 at 15:12
  • I use Synopsys, usually they are pretty good with keeping up. It could be an order thing... how does it know if an $error goes off in one file and a $info in the other, the order to print those in? – user5888527 Mar 11 '16 at 15:17
  • Actually without an initial block and condition it does print at elaboration time. Only problem is it marks it as a warning. – user5888527 Mar 11 '16 at 15:22
  • That seems like a bug to me. There's no way to control the ordering of elaboration messages. You should provide more details of why you are lokking for this behavior. $error/$fatal will cause the elaboration to stop anyways. – dave_59 Mar 11 '16 at 15:24
  • I tried it on [edaplayground](http://www.edaplayground.com/home), Works fine with all versions of Riviera-PRO, but cannot even compile with VCS 2014.12. I'm supersized it is not supported in 2014.12. Elaboration messaging was added in IEEE1800-2009 in § 20.10 _Elaboration system tasks_ (§20.11 in [IEEE1800-2012](http://standards.ieee.org/getieee/1800/download/1800-2012.pdf)) – Greg Mar 11 '16 at 18:33