Beaglebone and PRU, division and multiplication?

Question

Using the PRU of Beaglebone, how can I do a division and a multiplication?

Answer 1

Multiplication will be repeated addition of the first number to itself while the second number works as a counter.

Division will be repeated subtraction of the first number till the dividend becomes smaller than the remainder. You will also have a counter that you increment after every subtraction which will give your quotient.

Answer 2

The PRUs on the Beaglebone each have an accelerator (that is kind of a small coprocessor) for multiplication.

There are flags for the C/C++ compiler to enable automatic usage of the MAC for the TI compiler http://www.ti.com/lit/ug/spruhv7a/spruhv7a.pdf:

• --hardware-mac=on for using the MAC at all
• --fp_mode=relaxed for using the reciprocal when dividing by a constant

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For using assembler and doing it by hand:

See the Technical Reference Manual of the TI 335x (which is the processor on the Beaglebone) on chapter 4.4.1.3: http://www.ti.com/lit/ug/spruh73q/spruh73q.pdf

With the Xin/Xout instructions and using the intended registers, a 32bitx32bit=64bit multiplication can be quickly executed. Cf. chapter 4.4.1.3.2.1 for a step-to-step guide.

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The following is how you can do multiplication and division without an accelerator, but faster than just with addition/substraction:

You can do it, like you do it on paper

Multiplication of F0 x F1:

1. Bittest F0 for bit 0 and quick branch over next instruction (to 3.)
2. Add F1 to result
3. Shift F1 to the left by 1 bit
4. Bittest F0 for bit 1 and quick branch over next instruction (to 6.)
5. Add F1 to result
6. Shift F1 to the left by 1 bit
7. Bittest F0 for bit 2 and quick branch over next instruction (to 9.)
8. ...

Division of Q / D:

1. Shift D to the left (so that it still is inside the register)
2. Try to subtract D from Q (using a second register)
3. If successful, Q = Q - shifted D; if not Q unchanged
4. If successful, result | 1
5. shift result to the left by 1, shift D to the right by 1
6. repeat 1.-3. for remaining bit positions