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Say you have a signed 32bit number with a fraction length of 16bits. That is, the first 16 MSB are the integer part and the rest ( 16 LSB) are the fraction part. Is there a way in verilog to display this number number in base 10 that makes it easier to read decimals.

For example:

0000 0000 0000 0001 1000 0000 0000 0000 should be displayed as 1.5

I'm using Xillinx. I have looked online and I have not found a way to do this.

user3697625
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1 Answers1

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Use $itor integer to real to cast your binary pattern (integer). and use 2.0 (a real, not 2 an integer) to the power of (**) -16, the number of fractional bits:

module tb;
  initial begin
    $display("%g",$itor(32'b01_1000000000000000) * 2.0**-16);
  end
endmodule

On EDA Playground.

Morgan
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  • Thanks. Is there away to do that using monitor? Because when I use display in my testbench I get a value of 0. Even if I set a wait 30ns then display the value is zero. Only when I use monitor I get 0 then the expected value. – user3697625 Mar 02 '16 at 23:18
  • @user3697625 can you show your testbench, or minimal example which shows the problem. I do not think the problem is with `$display()` $monitor triggers when ever a value changes so it is likely that the display it not being requested at a time when the value is valid. – Morgan Mar 03 '16 at 08:52
  • :I have the test code on another questin that I'm awaiting an answer for: There is use $monitor() but if i switch to $display() i get a zero. Here is the link to the question and test bench:: [link](http://stackoverflow.com/questions/35735806/ways-to-implement-recipricals-on-verilog/35767951#35767951) – user3697625 Mar 03 '16 at 11:18