im unable to write output to text file in verilog .Please check what it is wrong

Question

module fir_tb;

    // Inputs
    reg clk;
    reg reset;
    reg [7:0] inp;
     reg [15:0]rom[1:8001];
    reg [15:0]addr=0;

    // Outputs
    wire [7:0] outp;

    // Instantiate the Unit Under Test (UUT)
    fir uut (
        .clk(clk), 
        .reset(reset), 
        .inp(inp), 
        .outp(outp)
    );




    initial 
  begin
      $readmemb("file_out_flute.txt",rom);
      reset=0;

      inp ='b0;
      #60;

      //$display("rom size is ",rom);
  end
  always @(posedge clk)begin
      inp = rom[addr]>>1;
      addr = addr + 1;
      if (addr==8000) ;//$finish;
  end
       initial 
  begin
      clk=1'b1;
      forever #10 clk=~clk;
  end


    integer f;
  initial begin
   f = $fopen("filter_output.txt","w");
     end

     always @(posedge clk)
     begin
     $fwrite(f,"%b\n",outp);

    $fclose(f);  


  end
endmodule

Answer 1

$fclose() closes the file; further writes will be usually be ignored. $fclose() is often on of the last operations you you want to call in an simulator; often just before a $finish statement.

integer f;
initial begin
  f = $fopen("filter_output.txt","w");
  #100; // <== simulation run time
  $fclose(f);
  $finish; // <== end simulation
end

always @(posedge clk)
begin
  $fwrite(f,"%b\n",outp);
end