Verilog blocking assignment not blocking

Question

I have a problem with Verilog blocking assignment, in the simulation it seems that it is not blocking. Espessialy in the second always@ block. I need the rst to go "1"only forv1 unit (clock cycle?), but it simultaneosly goes "1" and "0". When i replace bothrst = 1'b0; with rst = #10 1'b0; then in the simulation I can see the rst goes "1" for 10 units of time. Can anybody help me?

module testled(
input clk,
output reg out
);
 reg [23:0] counter;
 reg rst;


 initial begin
    out = 1'b0;
    rst = 1'b0;
    counter = 24'b000000000000000000000000;
end
always @(posedge clk, posedge rst) begin
    if(rst) begin
        counter = 24'b000000000000000000000000;
    end
    else begin
        counter = counter + 1;
    end
end

always @(posedge clk) begin
    case (out)
        1'b1 : begin
            if (counter[5]) begin
                rst = 1'b1;
                out = 1'b0;
                rst =1'b0;
            end
            else begin
                out = out;
            end             
        end
        1'b0 : begin
            if (counter[3]) begin
                rst = 1'b1;
                out = 1'b1;
                rst = 1'b0;
            end
            else begin
                out = out;
            end             
        end         
    endcase
end

endmodule

You need to use non-blocking (`<=`) assignments in ` always @(posedge clk) ` to correctly simulate the behaviour of a flip-flop. Trying to use the wrong type to get the behaviour you want will often result in a synthesis gates to RTL mismatch. There are ways to break this but you need to be very familiar with the implications of the code before you can use them safely. — Morgan, Feb 11 '16 at 13:16
Can you edit the question to describe the sequence your trying to generate. How long do you expect rst to go high for? — Morgan, Feb 11 '16 at 13:17
Doesn't even matter, because I just want to see how to generate "1"s and "0"s with different lenght — Kaarel Vandler, Feb 11 '16 at 17:32
well I wanted to program ws2812b LEDs and the bits in the datastream are combined with logic "1"s and "0"s with different length. I could't make these "1"s and "0"s with different lenght so I just wanted to understand how this works. — Kaarel Vandler, Feb 11 '16 at 20:13
The ws2812b data sheet kind of document is found on the link here http://www.seeedstudio.com/document/pdf/WS2812B%20Datasheet.pdf — Kaarel Vandler, Feb 11 '16 at 20:16

score 0 · Accepted Answer · answered Feb 11 '16 at 20:46

For simulation purposes you could do:

initial begin
  out = 1'b1;
  #10ns out = 1'b0;
  #20ns out = 1'b1;
  #30ns out = 1'b0;
end

But that is not synthesizable so will not help in your final application.

For sequential (clocked) logic the time high or low must be an integer number of clock cycles. Using Counter as an state and combinatorially decoding this for out.

always @(posedge clk,  rst) begin
  if(rst) begin
    counter <= 'b0;
  end
  else begin
    counter <= counter + 1;
  end
end

always @* begin
  if (counter < 10) begin
    out = 1'b0;
  end 
  else if (counter < 30) begin
    out = 1'b1;
  end
  else if (counter < 50) begin
    out = 1'b0;
  end
  else if (counter < 90) begin
    out = 1'b1;
  end
  else begin
    out = 1'b0;
  end
end

Verilog blocking assignment not blocking

1 Answers1