Tasktop.v(10): (vlog-2110) Illegal reference to net "b"

Question

I am writing a program in verilog. Total 3 AND Gates, the output of first 2 AND Gates is input to the 3rd Gate, and i am required the output of 3rd Gate. Please let me know what is the problem with my program. I am attaching my Program

//enter Top Module

module TOP;
wire a,b;
reg out;

initial
begin
#3 a=1;
#3 b=1;

#3 b=0;
end

Two_AND s(a,b,out);

endmodule


//.....................
//Main Program

module Two_AND (a,b,out);
input a,b;
output out;
reg out;


and g1(out1,a,b);
and g2(out2,b,c);
and g3(out3,out1,out2);


endmodule

Answer 1

In module Two_AND (a,b,out); you have these lines:

and g2(out2,b,c);

c is not defined.

out1, out2 and out3 are also not defined but are outputs and will be created as 1 bit wires by default which is ok in this instance.

but your output out is not driven, where you have used out3 you need to use out.

module Two_AND (
  input  a,
  input  b,
  input  c,
  output out
);

  wire out1,out2;

  and g1(out1,a,b);
  and g2(out2,b,c);
  and g3(out,out1,out2);
endmodule

Answer 2

@Morgan is right. However, the error you get is because there is something wrong with your TOP module. You should have defined a and b as reg and out as wire.

Only regs can be assigned within an initial or always block. And outputs of modules should be connected to wires.

Also, since an input c is added to your module, you should consider it while you are instantiating your Two_AND in your TOP module.

Answer 3

I think the previous answers were very instructive and helpful. I only want to add a small tip. I recommend you that always add `default_nettype none to your verilog codes. for example you have used "out1" and "out2" wires but you haven't define them. if you don't want to be confused, you should add that to your codes.