4-to-1 Multiplexer that implements addition, inversion, AND, OR gates on Verilog

Question

I just started learning Verilog this semester and I just got stuck on a task to create a Verilog module that has uses multiplexed to do different operations on 2 8-bit inputs. The below is the Verilog code that I wrote, I am getting several errors that I do not understand. Please help!

module eightbit_palu( input[7:0] a, input[7:0] b, input[1:0] sel, output[7:0] f, output ovf ); 

reg f, ovf; 
    always @ (a , b, sel)

    case (sel)
        0 : f = a + b;
            ovf = f[8]^f[7]; 

        1 : f[0] = ~b[0]; 
            f[1] = ~b[1]; 
            f[2] = ~b[2]; 
            f[3] = ~b[3]; 
            f[4] = ~b[4]; 
            f[5] = ~b[5]; 
            f[6] = ~b[6]; 
            f[7] = ~b[7];

        2 : f[0] = a[0]&b[0]; f[1] = a[1]&b[1]; f[2] = a[2]&b[2]; f[3] = a[3]&b[3]; f[4] = a[4]&b[4]; 
             f[5] = a[5]&b[5]; f[6] = a[6]&b[6]; f[7] = a[7]&b[7]; 

        3 : f[0] = a[0]|b[0]; f[1] = a[1]|b[1]; f[2] = a[2]|b[2]; f[3] = a[3]|b[3]; f[4] = a[4]|b[4]; 
             f[5] = a[5]|b[5]; f[6] = a[6]|b[6]; f[7] = a[7]|b[7];
    endcase

endmodule

The errors being displayed by the simulators are:

8: syntax error
10: error: Incomprehensible case expression.
11: syntax error
19: error: Incomprehensible case expression.
19: syntax error
22: error: Incomprehensible case expression.
22: syntax error

TERMINAL OUTPUT 8: syntax error 10: error: Incomprehensible case expression. 11: syntax error 19: error: Incomprehensible case expression. 19: syntax error 22: error: Incomprehensible case expression. 22: syntax error — KishTheMagnanimous, Jan 29 '16 at 03:41
Please edit your question to include this. Verilog is unknown to me, but the error messages you are getting are rather clear. Syntax errors mean the code is written incorrectly, look up what you're doing and see if you can spot difference. Incomprehensible case expression would mean that the way Verilog expects your code to be is incorrect too. I am betting remove the space before the colons, `1 :` becomes `1:`. — Marshall Davis, Jan 29 '16 at 03:45
I already tried that, it doesn't seem to make any difference when I change "1 :" to "1:". @ToothlessRebel — KishTheMagnanimous, Jan 29 '16 at 03:50

score 2 · Accepted Answer · edited May 23 '17 at 10:27

Two major issues:

First, with Verilog, a series of procedural statements must be surrounded by the begin-end keywords

always @ (*) begin
    case (sel)
        0 : begin
              f = a + b;
              ovf = f[8]^f[7]; 
            end

        1 : begin
            f[0] = ~b[0];
            ...
            end

        ...
    endcase
end

Second, you are mixing ANSI and non-ANSI style headers my declaring f and ovf as wires in the portlist, then single bit reg inside. Pick one syntax:

ANSI: (Note the output reg)

module eightbit_palu( input[7:0] a, input[7:0] b, 
  input[1:0] sel, output reg [7:0] f, output reg ovf );

Non-ANSI:

module eightbit_palu( a, b, sel, f, ovf );
  input[7:0] a;
  input[7:0] b;
  input[1:0] sel;
  output [7:0] f;
  output ovf;
  reg [7:0] f;
  reg ovf;

Suggested improvements:

always @ (a , b, sel) to always @*
- Since 2001, Verilog supports wild card sensitivity lists for combinational logic blocks. This helps prevent agents RTL vs synthesized-gates behavioral mismatches, and is the preferred coding style in Verilog. Defining the sensitivity manually is only required when strictly following the 1995 version of the standard.
you can simplfiy conditions 1, 2, and 3 to bitwise operations: (eg. 1 : f = ~b; , 2 : f = a & b;, 3 : f = a | b;). For-loops are another options
ovf is an inferred latch. Latches are not necessary bad, but you need to know what you are doing with them. It is recommended you use then only when necessary. What is inferred latch and how it is created when it is missing else statement in if condition.can anybody explain briefly?

4-to-1 Multiplexer that implements addition, inversion, AND, OR gates on Verilog

1 Answers1