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I'm looking to calculate cache miss/hit rates for some applications using Intel CPU event counters found here https://software.intel.com/en-us/node/589938

My question is why can I find cache events only for memory LOAD retired operations and not for store instructions too? A store instruction can also miss the cache at some point and should be included in the miss/hit rate.

The way I calculate the HIT rate for la L1 is: L1hit_rate=L1HIT_count/(L1HIT_count+L1MISS_count)

L1HIT_count=L1HIT_count_LOAD_INST+L1HIT_count_STORE_INST L1MISS_count=L1MISS_count_LOAD_INST+L1MISS_count_STORE_INST

user1934513
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  • I think the reason that the STORE events are missing is that a STORE event generates first a LOAD event to bring that location in the cache. Am I right ? – user1934513 Jan 26 '16 at 12:22
  • Maybe skylake has write-through write-around caches? Here's a reference for what that means https://en.wikipedia.org/wiki/Cache_(computing) – Tayyar R Feb 04 '16 at 21:48

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