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In assembly language under the instruction set of a 8085 microprocessor, suppose we have the following operation ADD B.
I know this means "Add the data of register of B to the Accumulator register and save the contents back to the Accumulator".

  • Here what is the mnemonic and what is the opcode.

  • ADD(only ADD and not ADD B) is the opcode or the mnemonic ?

  • Internally mneomonics are converted to hexadecimal codes such as 3E, so here what does this hexadecimal code refer to, ADD or ADD B.
    Kindly help.
Shivam Aggarwal
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  • look up mnemonic in the dictionary: "assisting or intended to assist memory". `add` is much easier to remember than 0x37 or whatever the actual numeric code for the operation is. `add` is the mnemonic, while for 8085, `add b` is a specific opcode, different from (say) `add a` or `add c`. – Marc B Jan 21 '16 at 14:47
  • @MarcB Please give me a direct answer . – Shivam Aggarwal Jan 21 '16 at 14:51
  • `ADD` is the mnemonic. The opcode is the instruction value that will be assembled into the program, and its value will depend on the addressing mode (if any) of the instruction. – Weather Vane Jan 21 '16 at 14:51
  • can't, because in this case, it's BOTH. intel x86/x85/etc... is a CISC instruction set, so there's specific opcodes for the SAME operation, but targetting different registers. you write `add b`, which maps to some numerical code. you write `add a`, and it maps to a different code, even though it's basically the SAME instruction. – Marc B Jan 21 '16 at 14:53
  • @MarcB Thanks. And the hexadecimal code which is mapped, is for the mnemonic or the complete opcode ? – Shivam Aggarwal Jan 21 '16 at 14:56
  • the complete instruction. never done 8085, but let's say `add a` is 0x3E, `add b` is 0x3F, `add c` is 0x40. like @sergeya said below, `add` is the mnemonic, and `a/b/c` are the operands, but for this particular CPU, it's the combo of BOTH that maps to a specific opcode. other (saner) instruction sets would op for a 2byte opcode. `add` being 0x10, and then a separate byte(s) to specify the target register. – Marc B Jan 21 '16 at 14:59
  • @MarcB Sorry to say but this confused me alot. – Shivam Aggarwal Jan 21 '16 at 15:03
  • The mnemonic is ADD, the opcode is 10000xxx, the instruction is 10000000 – Hans Passant Jan 21 '16 at 15:05
  • @HansPassant Is the instruction and opcode same here – Shivam Aggarwal Jan 21 '16 at 15:09
  • No, ADD C has the same opcode but a different instruction. The xxx bits select the operand. B = 0. – Hans Passant Jan 21 '16 at 15:12

3 Answers3

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Usually opcode refers to the type of operation (ADD), and register B is an operand. However, with a fixed and small number of operands, the same operation can have different opcode for all possible operands.

SergeyA
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The opcode refers to the binary sequence that identifies the instruction. So for the 8085 I believe 0x80 would be the opcode for "ADD B"

A mnemonic is a human readable name that helps you remember the instructions. So the string "ADD B" is a mnemonic for 0x80. "ADD B" is a lot easier to remember than 0x80.

zargothrax
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Some architectures have many different forms of the same mnemonic. Things should be much easier to understand when looking at an example from such an architecture.

e.g. x86 has 5 forms of 32bit add. (There are just as many forms for 8bit add, except of course that there isn't a 32bit immediate version. 16 and 64bit adds are encoded with prefix bytes in front of the 32bit encodings.)

Table format: OPCODE and operand encoding / MNEMONIC / OPERANDS (dest, src)

05 id ADD EAX, imm32    # special-case save-one-bye for adding to the accumulator

81 /0 id ADD r/m32, imm32
83 /0 ib ADD r/m32, imm8
03 /r ADD r32, r/m32    # src can be memory

01 /r ADD r/m32, r32    # dest can be memory

So for add eax, edx, there are two possible encodings: 01 D0 (picked by GNU as) or 03 whatever (looking up the encoding of the mod/rm byte for the operands in the other order is left as an exercise for the reader.)

The /0 means the unused src-reg bits in the mod/rm byte are borrowed as part of the opcode. 83 /4 ib is AND r/m32, imm8. When people say x86 machine code is nasty to decode, this is the kind of thing they're talking about (besides the variable-length nature, and the fact that optional prefix bytes mean the opcode isn't even the first byte... You have to mostly decode an instruction before you can even know how long it is to start decoding the next one. There's a reason parallel 4-wide decoding of x86 instructions is power-hungry.)

A more extreme case is that x86 uses mov for several different kinds of instructions, determined by the operands:

  • regular mov r32, r/m32 (or the reverse)
  • mov-immediate to register or memory
  • mov to/from segment registers (all three of these forms documented on the same page in the manual)
  • mov to/from control registers (even has a different entry in the manual)
  • mov to/from debug registers (another separate entry in the manual).

I can't think of a case where two different mnemonics produce the same opcode. But a single mnemonic can produce different opcodes with different operands.

The operand can even be encoded into the opcode byte for very commonly used instructions, to save space (this is SergeyA's answer). You could think of x86's B8 opcode as mov-imm32-to-eax. (the B8 to BF opcodes are all mov-immediate to register, each with a different destination reg.) 32bit x86 has single-byte opcodes for inc/dec of registers. x86-64 repurposed that contiguous range of 16 opcodes for use as REX prefix bytes (leaving the two-byte inc r/m32 form as the only option for inc eax.)

Peter Cordes
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