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I would like to know if there is a syntax in Verilog to access a wire in a sub-module without making that wire an output.

For example, if have the following modules: 

module Module_Sub(a,b);
   input a,b; 
   wire c; 
   ...
endmodule


module Module_Top(d, e);
   input d,e; 
   wire f; 

   Module_Sub sm(d,e); 
   ...
endmodule

Now, I want to access the wire 'c' in the instance 'sm' from the scope of Module_Top. Is there a way to do it? maybe something like: 

assign f = sm/c;

(This syntax obviously didn't work for me).

P.S: I know this isn't the best practice, but in my case it will make things a lot easier.

Thanks!

edit: I want it for a synthesis-able code.

Bamba
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  • Could you add via a question edit whether you want this for a Testbench, or synthesizable code. – Morgan Jan 15 '16 at 19:47

1 Answers1

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You were very close. Use dot, not slash:

module Module_Sub(a,b);
   input a,b; 
   wire c; 
endmodule

module Module_Top(d, e);
   input d,e; 
   wire f = sm.c; 

   Module_Sub sm(d,e); 
endmodule

Refer to IEEE Std 1800-2012, section 23.7 "Member selects and hierarchical names".

Greg
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toolic
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  • This does not seem to work. Sadly I don't have access to your reference document, but I try that and I get an error: "cannot resolve hierarchical name". Any thoughts? – Bamba Jan 15 '16 at 22:04
  • O.K I've found it, and also found a few more sources on the subject that contain examples. However it doesn't work for me. Is it synthesis-able? – Bamba Jan 15 '16 at 22:20
  • @Bamba Maybe you want to make wire c as output from module_sub. The solution of toolic will work otherwise (might not be synthesizable). Here's a similar question you can refer, to access resources outside module hierarchy: [Link](http://stackoverflow.com/questions/24591396/access-top-level-resources-outside-of-hierarchy) – sharvil111 Jan 16 '16 at 03:59