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I have been designing a Delta-Sigma DAC and have run into confusion and despair over the handling of signed numbers in my (sigma)counters and (delta and Vref) comparators.

I have tried to employ signed 2's complement but the EDAcompiler doesn't seem to notice when I do it, its most likely my own mistake!

So basically my question is, how (in Verilog) do I represent negative numbers in a way that they can be used in counters (which can therefore count up and down)? I am aware that a counter register that will hold signed numbers must be declared reg signed [:0]

Thanks! Gavin

toolic
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Andrew Davis
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    Please show some code. – Greg Jan 14 '16 at 20:12
  • What do you mean by 'employ signed 2's complement'? twos complement is a natural addition or subtraction. `sum = a-b; ` is all that should be required. Even if they are not declared signed twos compliment arithmetic is still performed.Adding a code example of what you have tried will help clarify. – Morgan Jan 14 '16 at 22:24

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Well I am not that clear on your question. Some compilers may not be able to handle signed registers directly since if I recall correctly it is a Verilog 2001 feature. But generally if you use digital logic that works with signed numbers you shouldn't have an issue. For example if you use an adder ip just mention that inputs are signed numbers. As for the simulator you can select the type of data you need, generally by selecting the register/value, right clicking on the waveform window and changing the type.

Finally if you have to create the logic yourself just use sign extension. so lets say you are working with 4 bit values

-5 would be 11111011 and 5 wold be 00000101. So you can see that for negative numbers the MSB is 1 and for positive its zero. Using this you can interpret the numbers in your code but just make sure that the size is bigger then what you want to use so no overflow occurs.

DBB
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  • Well by logic I meant the digital logic off the design like adder, multiplexer etc. Sorry about the confusion @EML – DBB Jan 15 '16 at 17:09