1

I have an existing verification environment with simple ports of length LEN. In addition, there are events,that occur when only one of the relevant port's bits rises:

  // Port declaration:
    port_a : inout simple_port of uint(bits:LEN) is instance;
    port_b : inout simple_port of uint(bits:LEN) is instance;
    ...

  // Events that use the ports for 1 monitor:
    event event_a is rise (smp.port_a$[idx:idx])@clock;
    event event_b is rise (smp.port_b$[idx:idx])@clock;

*** There are many monitors that every one has its own idx, event_a and event_b.

The problem is that I need to change LEN define to 64, and all events are now fail since Specman cannot define an event on bus of 64 bits (even though the events are actually "look" only on 1 bit..)

Do you have any idea how to workaround the issue? Thank you for any help.

Halona
  • 1,475
  • 1
  • 15
  • 26

1 Answers1

1

Actually, this form of defining an event is not supported:

event event_a is rise (smp.port_a$[idx:idx])@clock;

as bit slice in not supported inside a rise Temporal expression. (it is also documented in the ‘Event’ chapter in the ‘e language referene’.

In a case where you are interested in only one bit of this 64 bit signal you can instead define this port as simple_port of bit And put the bit slice in the hdl_path as follows:

idx:uint(bits:6);
keep idx==34; // the specific bit to this monitor.
port_a : in simple_port of bit is instance;
keep port_a.hdl_path()==read_only(append("signal_name[",idx,":",idx,"]"));

then define the event as :

event event_a is rise(port_a$)@sim;
yuvalg
  • 331
  • 1
  • 6