vhdl to verilog bintobcd converting

Question

Hello guys I am trying to translate following vhdl code to verilog however it does not work even if they look like pretty same. I get no errors however it is not working with verilog one but works with vhdl one. Can you guys please help me to work out this problem. :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity binbcd8 is

port(
b: in unsigned(7 downto 0);
p: out unsigned(9 downto 0)
);
end binbcd8;

architecture Behavioral of binbcd8 is

begin

bcd1: process(b)
variable z: unsigned(17 downto 0);
begin
for i in 0 to 17 loop
    z(i):='0';
end loop;

z(10 downto 3):=b;

for i in 0 to 4 loop
    if z(11 downto 8)>4 then
        z(11 downto 8):=z(11 downto 8)+3;
    end if;
    if z(15 downto 12)>4 then
        z(15 downto 12):=z(15 downto 12)+3;
    end if; 
    z(17 downto 1):=z(16 downto 0);
end loop;
p<=z(17 downto 8);

end process;    
end Behavioral;

to Verilog code and here is my code but it does not work. Can you please help me?:

 module binbcd8(input[7:0] b,output reg[9:0] p);
 reg[17:0] z;

 integer i;

 always@(b)
     begin
         z <=17'b0;
         z[10:3] <=b;
         for(i=0;i<4;i=i+1) begin
             if(z[11:8]>4)
                 z[11:8]<=z[11:8]+3;
             else
                 z<=z;
             if(z[15:12]>4)
                 z[15:12]<=z[15:12]+3;
             else
                 z<=z;
             z[17:1]<=z[16:0];
         end
         p<=z[17:8];
     end
 endmodule

Please clarify your question: What errors do you get? What is the expected output? — iled, Dec 19 '15 at 15:43
there is no error but it is not working when I put vhdl version of this code to top module it works correctly however when I put verilog version it is not working it only shows 0000 in seven segment with verilog code but shows distance correctly with vhdl one — fallen, Dec 19 '15 at 15:45
Duplicate of http://electronics.stackexchange.com/questions/206874/verilog-to-vhdl-bintobcd-converting. Please don't crosspost. — , Dec 19 '15 at 16:51

score 2 · Accepted Answer · edited Dec 19 '15 at 21:48

2

Your main problem is likely to be (a) that the VHDL loops 5 times (0 to 4) while the Verilog loops 4 times (for(i=0; i<4;...), and (b) that the Verilog code uses non-blocking assignments on z, where it should use blocking (z = x, not z <= x). Ask separately about that if you don't understand it.

Both sets of code could do with cleaning up. In the Verilog, your first assignment to z assigns 17 bits, not 18. The z <= z assignments are unnecessary. The VHDL uses a bizarre method to clear z - try variable z: unsigned(17 downto 0) := (others => '0');.

edited Dec 19 '15 at 21:48

Greg

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answered Dec 19 '15 at 17:09

EML

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I did not get the part (b) of my problems. Can you please explain it – fallen Dec 19 '15 at 17:25
by the way I implemented your suggestions on code and it did not work again – fallen Dec 19 '15 at 17:28
1

In the VHDL code, `z` is a variable, and it is evaluated *before* it is assigned to `p`. In the Verilog code, `z` has non-blocking assignments, so it is *not* evaluated before being assigned to `p`. The newly-calculated value is scheduled for a future update. Just look up blocking vs. non-blocking. If the mods don't work, then you'll need to post what output you're getting for a specific input, and what outputs you expect. – EML Dec 19 '15 at 17:34
No problem. Note also that the VHDL code uses both `std_logic_unsigned` and `numeric_std`, which isn't good - get rid of the `std_logic_unsigned`. – EML Dec 19 '15 at 19:54
ok also I want to ask you how can I do for instance sig<='Z' in verilog i googled it and it mainly says deassign sig however it is not acceptable by computer and how can I replace to_unsigned(d,d'length) in Vhdl while translating to verilog – fallen Dec 19 '15 at 20:45
Verilog is 4-state: `0`, `1`, `x`, `z`. Just assign `z` to your value. You have to be careful with the widths of the LHS and RHS; Verilog silently truncates or extends, whereas VHDL requires you to get it right. You can generally just ignore `to_unsigned` statements, and it will probably just work, since Verilog is basically typeless. – EML Dec 19 '15 at 21:20
then for instance if(x= to_unsigned(1000,26)) in vhdl must be written as if(x==26'd1000) in verilog? also when I assign to z it gives error – fallen Dec 19 '15 at 21:24

vhdl to verilog bintobcd converting

1 Answers1