What is an atomic operation in the context of microcontrollers?

Question

What is an "Atomic Operation" in the context of micro-controllers?

I am studying TI F28027 MCU.

The data sheet says that its operations are atomic. What does it mean?

Atomic (Greek) means that which cannot/should not be split into more pieces. In computing, an atomic instruction/operation means that which cannot/should not be interrupted (its lower-level steps be separated) while being executed, or there is risk of unwanted side effects. Interrupt disabling is the most crude way to force a series of instructions to behave almost as if they were 1. Under RTOS/multitasking, two or more tasks accessing the same variable need to read/update the variable in an atomic operation. This is done with semaphores, or by ensuring simultaneous access is not possible. — tonypdmtr, Dec 05 '15 at 09:00
Simple, universal definition: if you disassemble a high-level language instruction and it yields exactly 1 assembler instruction, it it atomic. If it yields more than 1 assembler instruction, it is not atomic. — Lundin, Dec 07 '15 at 07:19
@Lundin Not quite so. There are architectures with certain instructions that are interruptible. — tonypdmtr, Dec 07 '15 at 13:01

score 10 · Accepted Answer · answered Dec 05 '15 at 16:32

Read the Wikipedia article on atomic operations for a description of what "atomic" means generally. Here's the nutshell excerpt:

In concurrent programming, an operation (or set of operations) is atomic, linearizable, indivisible or uninterruptible if it appears to the rest of the system to occur instantaneously. Atomicity is a guarantee of isolation from concurrent processes.

The TI F28x Piccolo microcontroller family has a special Atomic ALU (arithmetic logic unit) that allows read-modify-write instructions to be performed atomically. This C2000 Piccolo Workshop document has some information. I believe special assembly syntax is required to take advantage of the atomic ALU (page 1-6). I suspect TI's Code Composer compiler will produce atomic assembly syntax when it can. Although how you write your C code may affect how efficient the compiler is (page 3-5).

Consider consulting TI's E2E Community for more help.

score 1 · Answer 2 · answered Dec 05 '15 at 06:36

I'm not familiar with that particular MCU, but typically, atomic operations are those that modify a memory location and no other context, hardware or software, can interrupt the read and susiquent write sub-operations. This guarantees that nothing else could change the memory location out from under the operation.

For example, an increment operator must read the target memory location, add one to the value, and then write back to the same location. If it were not atomic, something else might write to that same location between. Then when the write-back occurs, the intermediate write would be lost.

So what kind of other contexts are blocked by an atomic operation?

Interrupts where the ISR writes to memory.
DMA writes to RAM.
Other cores in a multi-core processor.

It's not specific for memory operation. It's any operation that couldn't be interrupted. — وليد تاج الدين, Dec 05 '15 at 15:03

score 1 · Answer 3 · answered Dec 07 '15 at 14:55

It generally has to do with resources or features for a resource that require/desire two (more than one) accesses and require those two accesses to not be interrupted by some other unrelated access. So a read-modify-write, or a test and set are two common examples.

If you didnt have any atomic or the kind of atomic you needed then you would in software have to insure that the two accesses are not interrupted or interfered if possible, if not possible then you need other solutions. Often hardware will give you at least one (like a test and set) from which you can create other protected features in software. The software solutions for example might be protecting a foreground task with an interrupt service routine, if the interrupt were to happen in between the two accesses (test and set, read-modify-write read and write being the two accesses) then the isr might modify the data after the first read but before the following write making the first read now stale/incorrect. So when protecting yourself from an interrupt you typically disable interrupts temporarily and then re-enable. Having the hardware do this it insures that even if an interrupt occurs or even if there is an other peripheral that has access, it is held off, and/or you are held off depending on priority, so your atomic operation can happen uninterrupted.

What is an atomic operation in the context of microcontrollers?

3 Answers3