Unwanted one clock delay vhdl

Question

can someone explain me why I have one clock delay on my simulation of the following and how can I fix it, it shouldnt be there cause I am missing a bit on the output....

entity outBit is
port(   clk1 : in STD_LOGIC; 
        clk2 : in STD_LOGIC;
      -- reset  : in STD_LOGIC;
        int_in : in INTEGER;
        bit_out : out STD_LOGIC); --_VECTOR of 32
end outBit ;

Is my entity and every rising edge of clk 1 it takes an integer. According to what integer it is(1, 2, 3, 4...) it chooses the corresponding line of an array. That line is of 32 bits. I want to output one bit of the 32 each clk2. For example if clk1 = 100 then clk2 = 100/32.

architecture Behavioral of outBit is
signal temp : array; --the array is fixed
signal output_bits : std_logic_vector(31 downto 0);
signal bit_i : integer := 31; --outputting a single bit out of 32 each time
begin

    temp(0) <= "11111111111111111111111111111111";
    temp(1) <= "11111111111111111111111111111110";
    temp(2) <= "11111111111111111111111111111100";
    -- etc 

output_bits <= temp(int_in);

    process(clk2)
      --outputting a single bit out of 32 each time
      --variable bit_i : integer := 31; 
      begin
        if rising_edge(clk2) then
          bit_out <= output_bits(bit_i);
          if bit_i = 0 then
            bit_i <= 31;
          else
            bit_i <= bit_i - 1;
          end if;
        end if;
      end process;
end Behavioral;

The unwanted delay is shown below. I would like each 32 cycles to read the new line (according to the input integer) and so on....

BY the way the firstclock (in code),(second clock in picture) is not really relative to the question is just to get the idea when the integer is coming

You need to show us how you generate Clk1 and Clk2 in the testbench. To be able to clock between them, they need to be phase aligned. — Jim Lewis, Nov 30 '15 at 18:46

score 1 · Accepted Answer · edited May 23 '17 at 12:07

If you want to get rid of the bit_out delay don't make it a flip flop:

library ieee;                      -- add missing context clause
use ieee.std_logic_1164.all;

entity outbit is
    port (
    --    clk1:       in  std_logic;  -- not relevant
        clk2:       in  std_logic;
     -- reset:      in  std_logic;
        int_in:     in  integer;
        bit_out:    out std_logic  --_vector of 32
    );
end entity outbit;

architecture behavioral of outbit is
    type bit_array is array (0 to 3) of std_logic_vector(0 to 31); -- added
    signal temp : bit_array; --the array is fixed -- non_reserved word name
    signal output_bits : std_logic_vector(31 downto 0);
    subtype index_int is  integer range 0 to 31;  -- changed bit_i type 
    signal bit_i: index_int := 31; --outputting a single bit out of 32 each time

begin

    temp(0) <= "11111111111111111111111111111111";
    temp(1) <= "11111111111111111111111111111110";
    temp(2) <= "11111111111111111111111111111100";
    temp(3) <= "11011001110000110101001000101110"; -- added
    -- etc 

    output_bits <= temp(int_in);

    process(clk2)
      --outputting a single bit out of 32 each time
      --variable bit_i : integer := 31; 
      begin
        if rising_edge(clk2) then
         --  bit_out <= output_bits(bit_i);   -- moved
          if bit_i = 0 then
            bit_i <= 31;
          else
            bit_i <= bit_i - 1;
          end if;
        end if;
      end process;

      bit_out <= output_bits(bit_i);           -- moved to here

end architecture behavioral;

Move the bit_out assignment outside the clock conditioned if statement. (It can be a concurrent signal assignment and represents a 32:1 multiplexer).

Add a test bench to complete a Minimal, Complete, and Verifiable example:

library ieee;
use ieee.std_logic_1164.all;

entity outbit_tb is
end entity;

architecture foo of outbit_tb is
    signal clk2:    std_logic := '1';
    subtype temp_index is integer  range 0 to 3;
    signal int_in:  temp_index := 3;
    signal bit_out: std_logic;
begin
CLOCK:
    process
    begin
        wait for 5 ns;  -- so can multiply clocks in my head to get stop time
        clk2 <= not clk2;
        if now > 360 ns then
            wait;
        end if;
    end process;
DUT:
    entity work.outbit
        port map (
            clk2 => clk2,
            int_in => int_in,
            bit_out => bit_out
        );
end architecture;

And the delay is gone:

Yeah I got it now. Thanks! And next time my question will be complete! ;) — Franx, Dec 04 '15 at 16:20

Unwanted one clock delay vhdl

1 Answers1