What is wrong with this Verilog code?

Question

I wrote a module that works as a counter (seconds) and displays the number on two seven segment displays on an Altera board, one for each digit.

Here is the module:

module assignment2_sevenseg(clkin, seg1_output, seg2_output);

input clkin;
output reg [6:0] seg1_output;
output reg [6:0] seg2_output;
reg currentTime;

assignment2_sec seconds(.clkin(clkin), .output_sec(currentTime));

always @(currentTime)   

begin


digitaltimer timer(currentTime/10, seg1_output);  //left segment (line 14)
digitaltimer timer1(currentTime%10, seg2_output); //right segment (line 15)

end

endmodule

The assignment2_sec module is another module used to count/increment the seconds. It should be working fine. The errors im getting are in the two lines between the begin/end statements in the always statement.

Error (10170): Verilog HDL syntax error at assignment2_sevenseg.v(14) near text: "("; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword.

Im also getting that exact error for line 15.

Here is the digitaltimer module too just for reference.

module digitaltimer(num , segments); 

input [3:0] num ; 
output [6:0] segments ; 
reg [6:0 ] segments ; 
always@(num)

begin 

case (num)

0: segments <= ~7'b0111111;
1: segments <= ~7'b0000110;
2: segments <= ~7'b1011011;
3: segments <= ~7'b1001111;
4: segments <= ~7'b1100110;
5: segments <= ~7'b1101101;
6: segments <= ~7'b1111101;
7: segments <= ~7'b0000111;
8: segments <= ~7'b1111111;
9: segments <= ~7'b1101111;
default: segments <= ~7'bx ;

endcase
end
endmodule

Answer 1

You are instantiating modules in an always block. As you've done with your assignment2_sec modules, you should instantiate modules "stand-alone", ie, not in any procedural block (such as always, initial, etc). Remove the always @(currentTime) begin and end and it should be fine (Im pretty sure the divide and modulo are fine as they are; but Im used to using at least SV-2005, not V2K as you are).

Also note in your digitaltimer module, first, use always @(*) instead of always @(num), using explicit sensitivity lists as you have done is an easy way to get into trouble. Secondly, using blocking assignment (=, not <=) in that block as it represents combinational logic. Only using NBA (<=) in sequential blocks (things like always @(posedge clk)). Finally, ~7'bx === 7'bx so you dont need to NOT it.

Answer 2

I don't think this is legal:

digitaltimer timer(currentTime/10, seg1_output);  //left segment (line 14)

You're trying to perform a mathematical operation while instantiating a module. You should perform the division and modulus operations separately with their own reg variables, then connect the output of those operations to the digitaltimer module.