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I want to write a code that counts backward from 9999 to 0630 and a reset button on FPGA Nexys3 when pressed the initial value will appear (9999).

Here is my block diagram:

block diagram

I have finished the slow-clock module but I don't know in which module should I write the reset code? and what should it be?

If I knew the code of the counter (project module) I would be able to write the rest modules.

Please help me in writing the counter code and the reset code.

sharvil111
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Moaedh Alwahidi
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    What have you tried so far? Please be elaborate. This can easily be accomplished by one reset logic with a single always block. – sharvil111 Nov 26 '15 at 15:41
  • Refer [this](http://www.asic-world.com/examples/verilog/up_down_counter.html) and [this](http://stackoverflow.com/questions/30667787/verilog-4-bit-up-down-counter-designed-using-negative-edge-triggered-t-flip-flop) links for up-down counters. You'll get an idea about down counter. – sharvil111 Nov 26 '15 at 16:27

1 Answers1

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The reset functionality should be such that the outputs and internal registers are assigned initial counter values.

The reset value is 9999. The counter should count down from 9999 to 0630 on every clock pulse. After reaching 0630, it gets reset and it can optionally give an out pulse indication.

Following is a sample code, this may not be the optimum version.

module ctr(counter,reset,clk)//out

output reg [13:0] counter; 
// output reg out; 
input reset;
input clk;
always @(posedge clk, negedge reset) begin 
if(!reset) begin
  counter <= 14'd9999; 
  // out<=0;
end 
else begin
  if (counter == 14'd0630) begin 
    counter <= 14'd9999; 
    // out <= ~out; 
  end 
  else begin 
    counter <= counter -1; 
  end 
end
end
endmodule
rahulcodesinverilog
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