How 32 bit IR hold load instruction?(RISC style 32bit architechture)

Question

I am bit confused with instruction size and addressable space (I assumed that instruction size should be same as size of address bits. I did not find enough explanation in my book)If I am correct, then in theory if we have a 2^32 addressable units(bytes) of memory in 32 bit architecture (RISC style) how a 4byte sized load instruction hold opcode as well as address?

Answer 1

You're assuming that a single instruction can encode a load from an arbitrary absolute address. This is true on x86, even in 64bit mode (but there's a special opcode for loading from a 64bit absolute address with no displacement or index register, and the dest must be rax).

On most RISC architectures, loading from an absolute address is typically done with two mov-immediate instructions to set the upper and lower half of a register, then use that register as the address for a load.

For example,

int a;
int foo(void) { return a; }

compiles to (ARM gcc 4.8.2 on godbolt):

foo():
    movw    r3, #:lower16:.LANCHOR0 @ tmp113,
    movt    r3, #:upper16:.LANCHOR0 @ tmp113,
    ldr r0, [r3]    @, a
    bx  lr  @
a:
    .space  4

Answer 2

For memory access instructions, the instructions typically use an address register with offset. Something of the form : load R1, [R2 + 8]. ARM, x86, MIPS and many others offer this mode. There is often the option to use PC as the address register, to be able to fetch constants that are next to the code.

For jump instructions, in addition to using an address register, you often have an offset jump, that don't use any register but jump X instructions forward or backward. The offset is usually limited in range, and may be shifted by some amount (restricting to addresses multiple of 2, 4 ...), so it can fit in a small immediate operand.
MIPS also use a mix between absolute and relative jump : the j instruction jumps to an absolute address, but in the region of the current instruction. To be precise, the immediate address is missing a few upper bits (so that it can fit), and use the upper bits of the current PC instead.

Answer 3

You can encode a 32-bit immediate value within a 4-byte instruction by limiting the amount of values that can be represented in the range.

ARM does this by encoding the immediate with 8 bits, plus an additional 4-bit field that specifies a rotation. The CPU calculates the immediate value by taking these 8 bits and shifting them the number of times indicated by the 4-bit field.

Answer 4

And one trick more (ARM also uses a version of this): if the instruction address must be 4-byte aligned, don't include the 2 lowest bits - they must be zero. You have now 2 bits for opcode.

And some processors don't support absolute addresses as immediates at all, just longish relative offsets. Those systems use trampolines for longer jumps.