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I'm working on a lab in Verilog and one of the tasks tells me to write different contents to 2 different addresses.

Here is my code:

module labM;

reg [31:0] address, memIn;
reg clk, read, write;
integer i;
wire [31:0] memOut;

mem data(memOut, address, memIn, clk, read, write);

initial
begin   
    write=1;
    memIn = 32'h12345678;
    address = 16;
    clk=1;
    #1;

    memIn = 32'h89abcdef;
    address = 24;
    #1;

    write=0; read=1; address=16;
    repeat(3)
    begin
        #1 $display("Address %d contains %h", address, memOut);
        address = address + 4;

    end

end

endmodule

mem works as follows:

In order to read a word, set its address on address and set read. After some delay, the word's content will become stable on memOut. To write, set the data to be written on memIn, set the destination address on address, and set write. The data will be written on the destination at the next positive edge of clk.

The output of the above is the correct value for address 16, but addresses 20 and 24 is "xxxxxxxx".

I've been stuck on this for a while, and I don't understand why I can't re-assign memIn.

Any help would be much appreciated.

Thanks.

Jongware
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M. Averbach
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  • From the testbench snippet, there is no write at address 20, so obviously `xxxx` is correct. **Showing** your `mem` module would be **useful**. Moreover, there is no posedge of `clk` while writing to address 24. How are you driving `clk`? Maybe `always #5 clk = ~clk` is a preferable method. – sharvil111 Nov 15 '15 at 03:36
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    @sharvil111 The problem is that the clock is not running (though I prefer `initial begin clk = 1'b0; forever #5 clk = ~clk; end`) so you should probably turn your comment into an answer. Also note that its best practice to use NBA in the `initial` block to mimic the behavior of the inputs coming from some external registers. – Unn Nov 15 '15 at 11:15
  • @Unn, Thanks, but why would you prefer initial/forever block for clock generation. I've read about time-zero event for clock oscillators, but found no specific reason for that. When my code can be of 20 alphabets, why waste more energy..? – sharvil111 Nov 15 '15 at 12:22
  • Maybe the difference lies in the data type. For me it's a `bit`, can be `logic` for you (rest of all interface signals are logic, only clock is bit). – sharvil111 Nov 15 '15 at 12:27
  • @sharvil111 Theres no real reason for it, I did have many clocks defined as `logic` for school projects, thus needed the `clk = 1'b0;` lines and just liked having everything in a single process. Just a stylistic choice. – Unn Nov 15 '15 at 13:04
  • @sharvil111 The thing is I set clk=1 in the beginning, so when I write to address 24 its still 1, same with write. For some reason its not writing to address 24. I cant show the module mem because its one built-in component on my school compiler. – M. Averbach Nov 15 '15 at 13:37
  • Exactly you set clk to 1. A clock needs to oscillate between 1 and 0, memories are normally edge sensitive not level. – Morgan Nov 15 '15 at 13:52
  • @Morgan Thank you so much. I set clk=0 and then set clk=1, and it worked. My problem was I didn't pay attention to the "edge sensitive" part of description. – M. Averbach Nov 15 '15 at 14:33

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