When dealing with 32 bit addresses and fully associative cache architecture, do we take away an offset from the address when comparing it with the tag of the cache, or do we take the full 32 bit address and compare it with the tag in the cache?
I am designing a cache simulator, and want to make sure I understood this portion right.
When your dealing with 32-bit addresses you use the bits from 31 to 5 for the tag and 4 to 0 for the offset. This means you're not taking all the address to compare with the tag. i.e. Address A[31:0] is splitter into tag A[31:5] and offset A[4:0]. For more information see https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Memory/fully.html
