Verilog with cocotb : assign statement

Question

My Verilog code is an adder that just uses assign sum = a+b. The problem is that, while running it using cocotb, sum remains unknown, though a and b have valid values.

When I make sum a reg type, it works.

`timescale 1 ns / 1 ps

module adder(input [7:0] a,
        input [7:0] b,
        output reg  [7:0] sum,
        output [7:0] sum2);

    assign sum2=a+b;        // Trouble is here
    always@(a,b) begin
        sum=a+b;            // This works
    end

`ifdef COCOTB_SIM
    initial begin
        $dumpfile("adder.vcd");
        $dumpvars();
    end
`endif
endmodule

score 5 · Accepted Answer · answered Nov 08 '15 at 17:28

5

I believe this is actually caused by a bug in Icarus present in v0.9.7.

If you upgrade to the latest development version you'll find that a continuous assignment works fine. Other simulators also handle the continuous assignment fine.

If you're stuck on that version of Icarus you can workaround it by putting the assignment inside a process, as you discovered.

answered Nov 08 '15 at 17:28

Chiggs

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I take it the waveform image apparently showing a Gtkwave windows clued you in to the use of Icarus? – Nov 09 '15 at 01:29
1

@user1155120 GTKWave is a giveaway, but a few people have also hit this issue. Unfortunately most of the repositories for popular Linux distributions still provide Icarus v0.9.7 – Chiggs Nov 09 '15 at 10:33
@Chiggs Hello Chris, I created the new tag [tag:cocotb], because there are more and more cocotb related questions and answers at SO. Maybe you want to subscribe to it. – Paebbels Mar 02 '16 at 16:30
@Paebbels thanks for that, will subscribe and try and help folks out where I can – Chiggs Mar 02 '16 at 21:47

Verilog with cocotb : assign statement

1 Answers1