VHDL Signal changes on the edge of two separate signals

Question

I was looking at this post Flip-Flop triggered on the edge of two signals

I have a similar problem, my circuit will have one signal act as a "Start" and another as "End" to control a transmitter. The logic is something like this:

if (start) then 
    running <= true 
else if (end) then 
    running <= false

The solution provided by "Marty" answers this problem. In one of his replies, "giroy" said: "I realize this is not the best way of doing it, but that is outside my control and i'm stuck working with it"

I am new to VHDL and wondering what is a better way of implementing the problem above

Possible duplicate of [Flip-Flop triggered on the edge of two signals](http://stackoverflow.com/questions/1301673/flip-flop-triggered-on-the-edge-of-two-signals) — Szabolcs Páll, Nov 06 '15 at 16:04
You may have to define 'better' and 'best' from your expectation. SO tends to discourage questions with those subjective-looking words. — Whirl Mind, Nov 06 '15 at 16:20

score 1 · Answer 1 · answered Nov 06 '15 at 21:24

You simply need a (clocked) RS-FF:

set = start
reset = end

Example code for a SR-FF:

process(Clock)
begin
  if rising_edge(Clock) then
    if (set = '1') then
      reg <= '1';
    elsif (reset = '1') then
      reg <= '0';
    end if;
  end if;
end process;

VHDL Signal changes on the edge of two separate signals

1 Answers1