Verilog program won't read input

Question

I've written this program in Verilog, but when I try to simulate it, it only shows XXXX... both on outputs and on input variables. I don't get what I've done wrong...

PS. In the simulation file i give, for example the value in = 16'b1101100100001111; #20; .

module hamming_decoder(
output reg [10:0] out,
output reg [3:0] error_index,
output reg error,
output reg uncorrectable,
input [16:1] in
);

reg y; // in case "single error", gives the position of the error bit    
reg [1:0] check; // if check[0] = 0 - no error
              // if check[0] = 1 and check[1] = 0 => double error
              // if check[0] = 1 and check[1] = 1 => single error


assign error_index[0] = in[16] ^ in[14] ^ in[12] ^ in[10] ^ in[8] ^ in[6] ^ in[4] ^ in[2];
assign error_index[1] = in[15] ^ in[14] ^ in[11] ^ in[10] ^ in[7] ^ in[6] ^ in[3] ^ in[2];
assign error_index[2] = in[13] ^ in[12] ^ in[11] ^ in[10] ^ in[5] ^ in[4] ^ in[3] ^ in[2];
assign error_index[3] = in[9] ^ in[8] ^ in[7] ^ in[6] ^ in[5] ^ in[4] ^ in[3] ^ in[2];

assign check[1] = in[1] ^ in[2] ^ in[3] ^ in[4] ^ in[5] ^ in[6] ^ in[7] ^ in[8] ^ in[9] ^ in[10] ^ in[11] ^ in[12] ^ in[13] ^ in[14] ^ in[15] ^ in[16]; 

always @(*)
begin
if (error_index[0] != 0 || error_index[1] != 0 || error_index[2] != 0 || error_index[3] != 0)
    begin
        check[0] = 1;
        error = 1;
    end

if (check[0] == 0)
    begin
        error = 0;
        uncorrectable = 0;
        out[0] = in[1];
        out[1] = in[2];
        out[2] = in[3];
        out[3] = in[4];
        out[4] = in[5];
        out[5] = in[6];
        out[6] = in[7];
        out[7] = in[9];
        out[8] = in[10];
        out[9] = in[11];
        out[10] = in[13];
    end
        else if(check[1] == 0)
                begin
                    error = 1;
                    uncorrectable = 1;
                    out[0] = in[3];
                    out[1] = in[5];
                    out[2] = in[6];
                    out[3] = in[7];
                    out[4] = in[9];
                    out[5] = in[10];
                    out[6] = in[11];
                    out[7] = in[12];
                    out[8] = in[13];
                    out[9] = in[14];
                    out[10] = in[15];
                end
            else if (check[1] == 1 && check[0] != 0)
                        begin
                            error = 1;
                            uncorrectable = 0;
                            y = error_index[0] + error_index[1] * 2 + error_index[2] * 4 + error_index[3] * 8;
                            out[0] = in[3];
                            out[1] = in[5];
                            out[2] = in[6];
                            out[3] = in[7];
                            out[4] = in[9];
                            out[5] = in[10];
                            out[6] = in[11];
                            out[7] = in[12];
                            out[8] = in[13];
                            out[9] = in[14];
                            out[10] = in[15];
                            out[y-1] = !out[y-1]; // ?
                        end
end

endmodule

sharvil111 · Answer 1 · 2015-11-04T15:56:25.353

This may be an issue related to testbench port connections. Are you sure about your test bench instantiation?

Also, to provide proper inputs, you need to have a clocking signal for periodic inputs otherwise all your inputs will travel in design at zero simulation time.

This sample 16'b1101100100001111 is shown as single error input data. It shall be great if you show your test bench also.

I've simulated your code and provided a test bench to it. Leaving the logic part, the design seems to be working fine. The testbench is available here.

EDIT:

Yes,your design is a combinational circuit. The conversion from input to output shall occur in zero simulation time. So, as soon as in occurs at 100ns, the value of out is computed and test ends abruptly. Just add in = 0 after 20ns delay and viola..!!

I've appended your test in the above EDAPlayground link, just added the above modification. This PDF about basics of test bench coding may be useful.

This is my Verilog Test Fixture file: `timescale 1ns / 1ps module hamming_decoder_test; // Inputs: reg [16:1] in; // Outputs: wire [10:0] out; wire [3:0] error_index; wire error; wire uncorrectable; hamming_decoder uut ( .out(out), .error_index(error_index), .error(error), .uncorrectable(uncorrectable), .in(in) ); initial begin in = 0; #100; in = 16'b1110101110001011; #20; end endmodule — francydarkcool -, Nov 04 '15 at 13:18
sorry: here is the file and a print screen of the result shown: http://we.tl/2ty5m8VbGZ — francydarkcool -, Nov 04 '15 at 13:22

Verilog program won't read input

1 Answers1