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I am new to vhdl and am attempting to write vhdl odd parity checker using Case within a process. When I compile there are no errors, but the output vector waveform for the output is flat for some reason. What am I doing wrong? Can someone assist me with this or point me in the right direction? Is there another way of doing this?

Here is my code:

library ieee;
use ieee.std_logic_1164.all;

entity test3 is 
port (
    w, x, y, z  : in std_logic;
    g1_562      : out std_logic);       
end entity test3;

architecture sig of test3 is

signal inputs : std_logic_vector(3 downto 0);
signal outputs: std_logic;
begin  

process(inputs) is
begin
case inputs is
    when "0000" => outputs <= '1';
    when "0011" => outputs <= '1';
    when "0101" => outputs <= '1';
    when "0110" => outputs <= '1';
    when "1001" => outputs <= '1';
    when "1010" => outputs <= '1';
    when "1100" => outputs <= '1';
    when "1111" => outputs <= '1';
    when others => outputs <= '0';
    g1_562 <= outputs;  
end case;
end process;
end architecture sig;

The output is: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

but should be: 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1

Thank you

Mac
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    What happens to signal inputs when you drive w, x, y, and z? – lasplund Oct 25 '15 at 17:35
  • Look closer at the assignment to g1_562. When is it executed? Also read about when signals like outputs are updated after an assignment. – lasplund Oct 25 '15 at 17:41
  • `g1_562` is assigned the current value of `outputs`. Signal values are never updated while the execution of any process is pending. Instead signals have a *projected output waveform* which can schedule updates for the current simulation time (with no time expression `after 0 fs` is assumed), which would insure the execution of a delta cycle with the new value of `outputs` available. The solution is to move the `g1_562` assignment outside this process (as in make it a concurrent signal assignment). –  Oct 25 '15 at 18:19
  • Thanks for the tips, solved! – Mac Oct 25 '15 at 18:22

1 Answers1

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Your signal inputs are never assigned to anything. You need a line outside the process where you concatenate the inputs w, x, y and z. Such as:

inputs <= w & x & y & z;

You should also move g1_562 <= outputs; outside the process.

anderswb
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