Synthesizing SystemC with Vivado doesn't give desired VHDL signals

Question

I am writing a project is systemC and i have a couple of sc_in<bool> and sc_out<bool> to communicate between my modules. When I synthesize the project, in the vhdl code produced each sc_in and sc_out creates a block of signals like this:

valid_in_address0 : OUT STD_LOGIC_VECTOR (2 downto 0);
valid_in_ce0 : OUT STD_LOGIC;
valid_in_we0 : OUT STD_LOGIC;
valid_in_d0 : OUT STD_LOGIC_VECTOR (0 downto 0);
valid_in_q0 : IN STD_LOGIC_VECTOR (0 downto 0);
valid_in_address1 : OUT STD_LOGIC_VECTOR (2 downto 0);
valid_in_ce1 : OUT STD_LOGIC;
valid_in_we1 : OUT STD_LOGIC;
valid_in_d1 : OUT STD_LOGIC_VECTOR (0 downto 0);
valid_in_q1 : IN STD_LOGIC_VECTOR (0 downto 0);

This is way too complicated as for my hardware design as I only want to have 1 signal declared like this:

valid_in : IN STD_LOGIC

Declaring a variable as sc_bit, I had no problem with the generated VHDL but after I tried using sc_in<sc_bit> instead of sc_in<bool> in my signals to communicate between modules the project does not compile anymore. If I assign values like this:

sc_bit asdf = 0;

I get the following message:

../../../../source.cpp:67:16: error: conversion from 'int' to non-scalar type 'sc_dt::sc_bit' requested

If I assign values like this:

sc_bit asdf = '0';

I get the following message:

../../../../source.cpp:68:14: error: no match for 'operator=' in '((source*)this)->source::asdf = '0''

Is there any other way to declare I/O signals in SystemC so that after synthesis I will only have 1 std_logic signal in VHDL?

The SC_MODULE for the source in the testbench goes like this

header file:

# ifndef SOURCE_H  
# define SOURCE_H  
# include "systemc.h"

using namespace std;

SC_MODULE(source) {    
    sc_in_clk clk;       
    sc_out<sc_bit > valid_out;           
    void do_cycle();       

    SC_CTOR(source) {        
    {       
        //irrelevant initializations
    }            

    SC_THREAD(do_cycle) {
        //i know sc_thread is unsynthesizable but source is testbench     
        //and i need the signal to be sc_out<sc_bit> to give it as            
        //input in my top function to be synthesized              
    }      
};          
#endif //SOURCE_H       

cpp file:

#include "source.h"          

void source::do_cycle() {          
    valid_out = '0';         
    while(true) {         
        wait(clk.posedge_event());       
    //do different kind of stuff         
    }   
}