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In Verilog, suppose I use the $size function on a 1-D vector. Would it give me the size of the value it holds or the size of the maximum value it can hold?

For example:

reg[10:0] a;
a=11'd3;
$display("Size of a is ",$size(a));

In this scenario, would it display "Size of a is 11", since this is the bit length of the max value that the vector can hold? Or would it say "Size of a is 2" since the actual bit length of the value in a, i.e, 3 is 2-bits?

P.S. I am new to verilog. So please excuse any syntax errors. Thank you

CodeMouse92
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QuickName123
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    Trying on a simulator (or several simulators) and find out. http://edaplayground.com has 9 options of 5 different online simulators. – Greg Oct 10 '15 at 03:08
  • Could you accept the best answer and upvote useful answers so that we know the question has been answered, thanks. – Morgan Oct 11 '15 at 10:06

1 Answers1

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According to my understanding, $size() gives the number of bits for a single dimension. Hence it should display 11. You can have a look at this answer https://stackoverflow.com/a/13345976/3951497 for more details.

Community
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ssgr
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  • I tried it out on ModelSim and `$size` and `$bits` don't seem to work. However I did some digging around and `$clog2` seems to work better. Thanks for all the help – QuickName123 Oct 10 '15 at 14:13