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On some architectures (e.g. x86) the Interrupt Vector Table (IVT) is indeed what it says on the tin: a table of vectors, aka pointers. Each vector holds the address of an Interrupt Service Routine (ISR). When an Interrupt Request (IRQ) occurs, the CPU saves some context and loads the vector into the PC register, thus jumping to the ISR. so far so good.

But on some other architectures (e.g. ARM) the IVT contains executable code, not pointers. When an IRQ occurs, the CPU saves some context and executes the vector. But there is no space in between these "vectors", so there is no room for storing the ISR there. Thus each "vector instruction" typically just jumps to the proper ISR somewhere else in memory.

My question is: what are the advantages of the latter approach ?

I would kinda understand if the ISRs themselves had fixed well-known addresses, and were spaced out so that reasonnable IRSs would fit in-place. Then we would save one indirection level, though at the expense of some fragmentation. But this "compact jump table" approach seems to have no advantage at all. What did I miss ?

Gyom
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2 Answers2

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Some of the reasons, but probably not all of them (I'm pretty much self educated in these matters):

  • You can have fall through (one exception does nothing, and just goes to the next in the table)
  • The FIQ interrupt (Fast Interrupt Requests) is the last in the table, and as the name suggest, it's used for devices that need immediate and low latency processing. It means you can just put that ISR in there (no jumping), and process it as fast as possible. Also, the way FIQ was thought with it's dedicated registers, it allows for optimal implementation of FIQ handlers. See https://en.wikipedia.org/wiki/Fast_interrupt_request
RuiFig
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  • thanks. I don't quite buy the fall-through argument, as having two vectors pointing to the same ISR would achieve the same effect. But the FIQ explanation does makes a lot of sense ! – Gyom Sep 29 '15 at 15:01
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I think it has do with simplifying the processor's hardware.

If you have machine instructions (jump instructions) in the vector interrupt table, the only extra thing the processor has to do when it has to jump to an interrupt handler is to load the address of the corresponding interrupt vector in the PC.

Whereas, if you have addresses in the interrupt vector table, the processor must be able to read the interruption handler start address from memory, and then jump to it.

The extra hardware required to read from memory and writing to a register is more complex than the required to just writing to a register.

Sergio Barrachina Mir
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  • Why does it need to jump to the PC address? Isn't JMP instruction just an instruction to modify the PC so that the next instruction is fetched from the new address? So, if the Interrupt Controller already fixed the PC (and flushed the pipeline, if you have one), then why can't we just let the CPU run and fetch the first instruction of the ISR? What is the jump there for? – Tammi Jul 12 '20 at 18:54
  • @Tammi jmp can be relative; not all platforms even support absolute jumps – SRobertJames Mar 11 '22 at 20:28