I have a FSM with 5 states. 3 of them are designed via sub-FSM(UML Pattern). For implementation in VHDL there are 2 ways, imho, to do that:
Summarize them into one, so I have a documentation with sub-FSM's and a product with one big FSM.
Build one FSM with all states. For every state which have a sub-FSM build a standalone FSM with enable signals from the big one.
This is no question about what's better, I think both ways have their advantages and disadvantages. But which way is more "clean" for VHDL implementation?
type my_big_one is (ONE,TWO_one, TWO_two, THREE_one, THREE_two, FOUR,FIVE);
vs.
type my_one is (ONE, TWO, THREE, FOUR, FIVE);
type two_fsm is (TWO_one, TWO_two);
type three_fsm is (THREE_one, THREE_two);