1

I have the following code, file c.sv:

virtual class C#(parameter W = 32); // line #2 where error message points
    static function logic [W-1 : 0] f(input logic [W-1 : 0] in);
        return ~in;
    endfunction
endclass

I then call it from top.sv:

`include "c.sv"
module top(input wire [3:0] key, ouptut wire [3:0] led);
    assign led = C#(4)::f(sw);
endmodule

In ModelSim 10.3d it works fine, but Quartus II x64 15.0.1 build 150 reports this error after Analysis & Synthesis:

Error (10170): Verilog HDL syntax error at c.sv(2) near text "virtual"; expecting a description

If I comment out inlcude "c.sv" and replace function call with a simple ~led then it works in the dev board.

What am I doing wrong?

Qiu
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Mishka
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1 Answers1

3

Sadly, there is no way currently to support parameterised functions in Altera Quartus. You have the following courses of action available:

  1. Raise a support ticket with Altera
  2. Use a third-party synthesis tool and feed the netlist into Quartus
  3. Re-factor your code to be less generic

Option 2 will of course involve forking out a non-trivial sum of money. Synopsys Design Compiler supports this construct, your mileage may vary with other tools.

For option 3 you could resort to macros, generated code or optional file compilation to achieve a similar result.

It's somewhat depressing that this capability isn't available to Altera FPGA users. For the benefit of the community please raise a ticket regardless of the course of action you choose. The more demand there is, the more likely Altera are to implement this feature.

There is some more discussion and prototyping of possible work-arounds that don't involve classes on the "Width independent functions" question.

Community
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Chiggs
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  • BTW, The `let` construct is intended to define _typeless_ functions so you could write `let f(in) = ~in;` without the use of classes or parameterization. I believe this is not supported by Quartus yet either, but I think they would have a better chance of implementing this first. – dave_59 Sep 09 '15 at 08:06
  • @dave_59 indeed the `let` construct would be very useful! Sadly FPGA vendors don't appear to have *any* appetite for implementing SV beyond what they have already. The joys of #semiEDA... – Chiggs Sep 09 '15 at 10:30
  • The wishlist of features that should be synthesizable, reminds me of the [2014-DVCon ASIC-FPGA SV Synthesis](http://www.sutherland-hdl.com/papers/2014-DVCon_ASIC-FPGA_SV_Synthesis_paper.pdf) paper. The appendix has a table comparing pseudo-anonymous synthesizers to a short feature list. I would like to see a more excessive list including `let`, `foreach`, attributes `(* *)`, `config`–`endconfig`, maybe even `alias` and array reduction methods (`.sum`, `.product`) – Greg Sep 09 '15 at 17:18
  • @greg indeed. It would be nice to define a "synthesisable subset" and have some kind of defined test-suite to certify as "SV" compliant. As things are, I suspect HLS will overtake SV before many of the innovative features are ever implemented or widely used. Vendors treat SV as syntactic sugar, which is a waste and holds back the pace of development... – Chiggs Sep 09 '15 at 21:38