1

Suppose there is a structure declared as:

typedef logic [7:0] Data;
typedef struct packed {
    logic valid;
    Data data;
} MyStruct;

An array of the struct is declared as:

MyStruct foo [8];

Is there a way other than using for loop to extract a field from all the array elements and form its own array/bit-vector?

In other words, I'm hoping to do something like this, which unfortunately doesn't seem to be valid SV syntax.

assign all_valid =  & foo[7:0].valid;
ohcamel
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1 Answers1

3

You can't slice an array like this in SystemVerilog, but because you are trying to do a reduction, there is a array manipulation method that you can use:

assign all_valid =  foo.and() with (item.valid);

See Section 7.12.3 Array reduction methods in the 1800-2012 LRM.

dave_59
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