2

I'm converting some verilog code to SC. Here is a case made me confused: In verilog, a continuous assignment such as:

wire a;
assign a =1;

Where a will get 1 immediately after the assignment. If we write it in SC:

sc_signal<bool> a;
a.write(1);

The current value of a will not be 1. How to resolve this problem? Like the following?

bool a;
a = 1;
swgchlry
  • 71
  • 4

1 Answers1

4

In Verilog, you are not guaranteed to read the updated value of a continuous assignment if you are changing the RHS and reading the LHS in two different processes synchronized to the same time. You need to use a non-blocking assignment to avoid a race condition.

In SystemC, the write() method is similar to a non-blocking assignment. The difference is that you are required to use the write() method in SystemC. So .you should only be writing to signals as the output of a thread/process. If you need to read the signal within the process, then you need to use a variable local to the thread.

dave_59
  • 39,096
  • 3
  • 24
  • 63
  • You are right, I think. Thx. I found SC is harder than verilog, though I'm familar with C++. – swgchlry Sep 06 '15 at 00:24
  • 1
    They are different languages with different strengths and weaknesses. Trying to convert line-by-line is what is difficult. BTW, please accept this answer by marking it. – dave_59 Sep 06 '15 at 15:42