OMAP5432 evm processor clock cycle

Question

I'm writting a linux driver for OMAP5432 (Cortex A15) which reads the processor cycle counter value to each IRQ. The counter is initialized like this :

static inline void init_perfcounters(int32_t do_reset, int32_t enable_divider) 
{
    // in general enable all counters (including cycle counter)
    int32_t value = 1;

    // peform reset:
    if (do_reset) {
        value |= 2;     // reset all counters to zero.
        value |= 4;     // reset cycle counter to zero.
    }

    if (enable_divider)
        value |= 8;     // enable "by 64" divider for CCNT.

    value |= 16;

    // program the performance-counter control-register:
    asm volatile ("MCR p15, 0, %0, c9, c12, 0\t\n" :: "r"(value));

    // enable all counters:
    asm volatile ("MCR p15, 0, %0, c9, c12, 1\t\n" :: "r"(0x8000000f));

    // clear overflows:
    asm volatile ("MCR p15, 0, %0, c9, c12, 3\t\n" :: "r"(0x8000000f)); 
}

The divider is disable. The Linux kernel is 4.0, frequency scaling option is disable and only 1 CPU is running. I have an IRQ every second and I read the value like this :

static inline unsigned int get_cyclecount(void)
{
  unsigned int value;

  // Read CCNT Register
  asm volatile ("MRC p15, 0, %0, c9, c13, 0\t\n": "=r"(value));  
  return value;
}

I don't understand why the number of cycles between two IRQ is of the order of 20M while the processor is supposed running at 2GHz. Anyone have any ideas ?

Thank you in advance.