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Why can't we design a (semi)pipelined processor that issues instruction at every alternate clock tick, instead of the pipelined processor that issues instruction at every clock tick? Having the instructions wait would probably reduce the hazards and stalls that we try to solve in a complicate way. It could completely eliminate the branch stalls and thus save the expensive pipeline flush.

Akhilesh
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You answered your own question in the comments. You could design one, but you're essentially sacrificing potential performance in order to simplify your design. A slight variation on what you're suggesting is something called a barrel processor. Each cycle the processor takes one instruction from a different thread and this allows the pipeline to be simplified. The HEP architecture is another variant on this idea.

hayesti
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