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I'm trying to set ARM cortex R5f processor stack on TCM to measure processor performance. but each time the stack accessed, to processor goes to abort handler.

when I write data on address 0x41000000 (BTCM) I got no error.

I got the following status registers :

CP15_DFSR = 0x800

SD axi_decode_error RW : write_access_abort

 CP15_IFSR = x0000

SD axi_decode_error

CP15_DFAR = 0x40FFFFF4 

Holds the address of the fault when a synchronous abort occurs.

BTCM configuration

; The Cortex-R5 has
; 4K BTCM from 0x41000000 to 0x41000FFF 
        MRC p15, 0, r0, c9, c1, 0       ; Read BTCM Region Register
        ; r0 now contains ATCM size in bits [6:2]
        BFC     r0,#12,#20
        ORR r0, r0, #1                  ; Enable it
        LDR     r1, =||Image$$BTCM$$Base||
        ORR r0, r0, r1                  ; Set BTCM base address
        MCR p15, 0, r0, c9, c1, 0       ; Write BTCM Region Register

MPU configuration

 ; Region - BTCM
        ADD     r1, r1, #1
        MCR     p15, 0, r1, c6, c2, 0       ; Set memory region number register
        LDR     r2, =||Image$$BTCM$$Base||
        MCR     p15, 0, r2, c6, c1, 0       ; Set region base address register
        LDR     r2, =0x0 :OR: (Region_4K << 1) :OR: Region_Enable
        MCR     p15, 0, r2, c6, c1, 2       ; Set region size & enable register
        LDR     r2, =0x0 :OR: (Full_Access << 8) :OR: Normal_nShared
        MCR     p15, 0, r2, c6, c1, 4       ; Set region access control register

configure stack

 MOV R1, 0x4100000 ;------------------------ set stack @ in BTCM -------------------  0x41001000
    ADD R1, R1, 0x1000


; Set up UNDEF registers
    mov     r0, #ARM_MODE_UNDEF:OR:I_BIT:OR:F_BIT
    msr     CPSR_cxsf, r0
    mov     r13,r1
    mov r14, #0
    msr spsr_cxsf, r6
    sub     r1,r1,#UNDEF_STACK_SIZE

; Set up ABORT registers
    mov     r0, #ARM_MODE_ABORT:OR:I_BIT:OR:F_BIT
    msr     CPSR_cxsf, r0
    mov     r13,r1
    mov r14, #0
    msr spsr_cxsf, r6
    sub     r1,r1,#ABORT_STACK_SIZE

; Set up Fast Interrupt registers
    mov     r0, #ARM_MODE_FIQ:OR:I_BIT:OR:F_BIT
    msr     CPSR_cxsf, r0
    mov     r13,r1
    mov r8, #0
    mov r9, #0
    mov r10, #0
    mov r11, #0
    mov r12, #0
    mov r14, #0
    msr spsr_cxsf, r6
    sub     r1,r1,#FIQ_STACK_SIZE

; Set up Interrupt registers
    mov     r0, #ARM_MODE_IRQ:OR:I_BIT:OR:F_BIT
    msr     CPSR_cxsf, r0
    mov     r13,r1
    mov r14, #0
    msr spsr_cxsf, r6
    sub     r1,r1,#IRQ_STACK_SIZE

; Set up supervisor registers
    mov     r0, #ARM_MODE_SVC:OR:I_BIT:OR:F_BIT
    msr     CPSR_cxsf, r0
    mov     r13,r1
    mov r14, #0
    msr spsr_cxsf, r6
    sub     r1,r1,#SVC_STACK_SIZE

; Set up System registers
    mov     r0, #ARM_MODE_SYS:OR:I_BIT:OR:F_BIT
    msr     CPSR_cxsf, r0
    mov     r13,r1
    mov r14, #0

jump to main

B main
bouqbouq
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  • What do the *FSR/*FAR registers have to say about the abort? Even just knowing the syndrome (e.g. external abort vs. permission fault) should narrow things down significantly. – Notlikethat Jul 27 '15 at 07:49
  • @Notlikethat I posted the status register in the question. any clue? – bouqbouq Jul 27 '15 at 08:20
  • @Notlikethat it worked just by putting `mov r1, #0x40001000 mov r13, r1`insteed of `mov r1, 0x40001000 mov r13, r1` . the `#`made the difference. what's the difference here?? – bouqbouq Jul 27 '15 at 08:47
  • Well, from the fault address you've clearly run off the bottom of the TCM - how big are all those *_STACK_SIZE constants? – Notlikethat Jul 27 '15 at 09:08

1 Answers1

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Either your total "STACK_SIZE" constants are bigger than your TCM, or your program is using more than STACK_SIZE bytes and running over its assigned space. The fault is because you are trying to access below your TCM address.

solidpixel
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  • in fact it worked just by putting `mov r1, #0x40001000` `mov r13, r1`insteed of `mov r1, 0x40001000` `mov r13, r1` . the #made the difference. do you think it may be the problem???? – bouqbouq Jul 28 '15 at 08:31
  • Probably - you need the "#" to make it see a literal constant. – solidpixel Jul 28 '15 at 08:33