verilog, FSM, finite state machine ,error

Question

When I simulate the below module in Modelsim, I did not see any output wave for cikis, please let me know what went wrong with this FSM and test-bench.

I have 3 input and 1 output for the module.

    module sayici_fsm( clock, reset,cikis, out);

    input  wire clock;
    input  wire reset;

    output reg  [2:0] cikis;
    output wire       out;

    localparam durum0 = 3'd0,
               durum1 = 3'd1,
               durum2 = 3'd2,
               durum3 = 3'd3,
               durum4 = 3'd4,
               durum5 = 3'd5,
               durum6 = 3'd6,
               durum7 = 3'd7;

    reg [2:0] currentstate;
    reg [2:0] nextstate;

    assign out = (durum1& durum3);

    always @(*) begin
        cikis = 3'b000;
        case (currentstate)
            durum0: 
            begin
                 cikis = 3'b000;
            end
            durum1: 
            begin
                cikis = 3'b000;
            end
            durum2: 
            begin
                cikis = 3'b010;
            end
            durum3: 
            begin
                cikis = 3'b100;
            end
            durum4: 
            begin
                cikis = 3'b110;
            end
        endcase
    end

  always @(posedge clock)  begin
    if(reset)  currentstate <= durum0 ;
    else       currentstate <= nextstate;
    end

  always @(*) begin
    nextstate =currentstate;
      case (currentstate)
        durum0: 
          begin
            nextstate = durum1;
          end
        durum1: 
          begin
            nextstate = durum2;
          end
        durum2: 
          begin
            nextstate = durum3;
          end
        durum3: 
          begin
            nextstate = durum4;
          end
         durum4: 
           begin
             nextstate = durum1;
           end
         durum5: 
           begin
             nextstate = durum0;
           end
         durum6: 
           begin
             nextstate = durum0;
           end
          durum7: 
            begin
              nextstate = durum0;
            end
        endcase
    end    
    endmodule

module sayici_fsm_tb();

wire [2:0] cikis;
wire       out;

reg clock;    
reg reset;    

sayici_fsm u1(.out   (out  ),
              .clock (clock),
              .cikis (cikis),
              .reset (reset)
             );

initial 
begin
    $display( $time,  "Similasyon Baslasin");
    $display( " Time  clock reset  enable giris cikis");
    $monitor ("time =%d, clock =%b, reset=%b, cikis=%b  out =%b", $time, clock, reset, cikis,out);

    reset = 1'b1;
    clock = 1'b0;
#5  reset = 1'b0;
    clock = 1'b1;
#100 $finish;  
end

always #7  clock =!clock;

endmodule

Do you see a clock in you modelsim waveform ? – TM90 Jul 24 '15 at 09:32 — TM90, Jul 24 '15 at 09:32

score 2 · Answer 1 · answered Jul 24 '15 at 10:03

The error is in the generation of reset in the testbench, since not properly initialized cikis goes to default value 'x'

     reset = 1'b1;
     clock = 1'b0;
  #5 reset = 1'b0;  // give more time  so that at posedge of clk reset is asserted say #8
     clock = 1'b1;  // remove from tb
  #100 $finish;  
end
always #7  clock =!clock;

From the above snippet the reset is going low at 5 ns but the clock is getting the first posedge at 7 ns, during posedge of clock the current state is coded to get the value of durum0 as mentioned below

always @(posedge clock)  begin
if(reset)  currentstate <= durum0 ;
else       currentstate <= nextstate;
end

To resolve the error wait for considerable amount of clock to and reset the bus.

verilog, FSM, finite state machine ,error

1 Answers1