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What is the significance of changing the duty cycle in i2c protocol? the feature is available in most of the advanced microcontrollers.

dennis menace
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  • duty cycle or frequency? can you post the part number for one/some of these microcontrollers? shouldnt make a bit of difference to the i2c slaves so long as neither half of the clock is within the spec of that part. – old_timer Jul 13 '15 at 13:28
  • I am asking about the duty cycle not the frequency. LPC1768, stm32F4xx are examples of the controllers which allow varying duty cycle feature. – dennis menace Jul 16 '15 at 08:39
  • This question belongs on electronics.stackexchange.com – psmears Jul 23 '15 at 12:13

1 Answers1

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The duty cycle is significant, because different I²C modes have slightly different duty cycle.

Check the I²C Specification v5 Table 10, pg. 48.

     Mode     | t_HIGH | t_LOW | ratio
--------------+--------+-------+-------
Standard-mode |  4.00u |  4.7u | 0.85
Fast-mode     |  0.60u |  1.3u | 0.46
Fast-mode Plus|  0.26u |  0.5u | 0.52

Your controller would need to decide on one ratio in order to be within the I²C specification.

So for instance, if the controller is using the standard mode timing ratio, this would prevent you from achieving fast mode timings with maximum clock frequency.

These are the ratios as defined in the standard for minimal t_HIGH:t_LOW. However, notice that the 100 kHz period is 10 us, but t_HIGH + t_LOW from the table is less than 10 us. Thus, the ratio of the actual values can vary as long as the t_HIGH and t_LOW minimum timings are met.

The point of these ratios is to illustrate that I²C timing constraints are different between I²C modes. They aren't mandatory ratios that controllers need to keep.

For example, 4 us high, 6 us low would be a 0.67 ratio, yet Standard-mode timings would be met.

STM32F4 example:

The STM32F4xx series only supports 100 kHz and 400 kHz communication speeds (RM0090, rev 5, pg. 818, Section 27.2).

I don't know where your ratios come from, but the reference manual states (RM0090, rev 5, pg. 849, Section 27.6.8) a 1:1 ratio for standard mode, and 1:2 or 9:16 ratio for fast mode.

So for instance, to achieve the highest standard mode clock frequency of 100 kHz, t_HIGH and t_LOW need to be programmed for 5 us, because the ratio is 1:1.

For Fast-mode, for example with a 1:2 ratio, you would need to program t_HIGH to 3.33 us and t_LOW to 6.66 us for 100 kHz. Yet that would not meet timing requirements for Standard-mode.

So you cannot use STM32F4 programmed for Fast-mode while keeping Standard-mode timings at highest Standard-mode frequency.

And vice versa: You cannot use Standard-mode and program 400 kHz Fast-mode, because the default 1:1 ratio is out-of-spec for 2.5 us, because t_LOW would be 1.25 us < 1.3 us.

psmears
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FRob
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  • Also I read the datasheets of some I2C slave devices, which shows different duty cycles for each device. Could this too be a reason. – dennis menace Jul 18 '15 at 07:11
  • However STM32F4xx series allows for only 2 duty cycles i.e 16/25 and 2/3 in fast mode. How do you manage the above duty cycles in that case? – dennis menace Jul 18 '15 at 07:15
  • @dennismenace I expanded my answer to accommodate your questions about STM32F4 and also to clear some things up about the ratios I put in my answer. – FRob Jul 23 '15 at 12:07