2

We all know that MIPS FPU has two precisions, single or double. When I looked it in the instruction set, I found for a same operation, the instruction for single precision and double precision have no different.

For example, here from the MIPS Architecture For Programmers Volume II: , the instruction ADD.fmt enter image description here

No matter it is double or single precision, the operand and function code are both same. How decoder know it is a single or double precision instruction? Or any hidden information in the 5-bit fmt region? I can not find any good answers from google, can someone explain how this instruction works?

Shuaiyu Jiang
  • 239
  • 1
  • 3
  • 15

1 Answers1

3

The MIPS documentation has details on this, under "FPU Operand Format Field". The fmt field contains that specific data.

The fmt field is 5 bit length and it can take the following values:

0-15: reserved
16: single
17: double
18-19: reserved
20: word
21: long
22-31: reserved

Word and Long are Unimplemented for ADD.S and ADD.D.

karatedog
  • 2,508
  • 19
  • 29
  • The fmt region in instruction ADD.fmt is only 5-bit. But in your answer the fmt contains totally 32-bit register. Is that fmt is a seperated register or something? When we implement this instruction, is the hardware of two different precisions same? I mean if a FPU support double precision, then the hardware is for double precision and no matter the instruction is single or double. – Shuaiyu Jiang Jul 10 '15 at 10:25
  • I wrote "possible **values**", not bit positions. 5 bit is 0-31. – karatedog Jul 11 '15 at 00:32
  • @ShuaiyuJiang I updated the answer to avoid further confusion. – karatedog Jul 11 '15 at 19:32