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I have a Testbench that uses VHDL-2008's hierarchical accesses to test the good behaviour of my architecture, which I wrote in VHDL.

Like this :

TEST_SIGNAL  <= << signal uut_0.signal_to_test : std_logic_vector(7 downto 0) >>;

This worked great but now what I want is to use the same testbench to simulate a verilog netlist corresponding to my synthesized design :

  • VHDL Testbench

    • Verilog netlist
    • Corresponding library

However, my hierarchical accesses don't work now ("Target of VHDL external name is not a vhdl object." error).
This is normal (I guess) but do you have any idea how I could work my way around this, i.e. still observe internal entities of my design? (Other than declaring everything I want to watch as outputs of my UUT...)

(I use ModelSim SE 10.3c to simulate)

Russell
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DylanM
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    Try looking at Modelsim's Signal Spy functionality. That should go across languages. – Russell Jul 06 '15 at 15:37
  • I was quite reluctant to use a ModelSim-specific feature but it looks really convenient so I will give it a try. Thanks for the tip. – DylanM Jul 08 '15 at 07:40
  • yes, I have used Signal Spy in the past, but I try to avoid it these days. In general I would recommend not writing your testbenches in such a way that you rely on drilling down the hierarchy to peek and poke internal signals. If you can avoid doing that it makes your life so much easier. – Russell Jul 08 '15 at 13:13
  • I used Signal Spy, it worked well for a little more than a week and then I needed to run some simulations in Cadence. I found that Incisive offers a very similar function that I could have used but I just ended up deleting all hierarchical accesses. It's a shame because it allows for much less verification (for internal memories for example) but it's a mess to use. Plus checking internal vectors in a synthesized (and therefore simplified) architecture can be quite a nightmare. (So I would advise to use hierarchical accesses only for early-stage debug purposes.) – DylanM Jul 20 '15 at 16:36

0 Answers0