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I am working a Verilog project for a digital design class and my project was to create a calculator that, amongst other things, takes the complement of a 16b signed input and displays it in decimal form in the monitor in the simulator.

This is my test bench monitor:

$monitor ("opCode(%b),in1(%d),in2(%d),result(%d),overflow(%b)", opCode, in1, in2, result, overflow);

I cannot get the simulator to display the complement of my input in negative decimal representation. Is this just something the simulator wont show, or an issue with the $monitor? All other results are being displayed as a decimal correctly.

The result displays like the below output. It shows the complement result displayed as 65526, which should be a -10. The results above and below are displayed correctly 15 and 11 respectively.

opCode(0111),in1(10),in2(5),result(15),overflow(0)
opCode(1000),in1(10),in2(5),result(65526),overflow(1)
opCode(1001),in1(10),in2(5),result(11),overflow(0)
Qiu
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jrmcdonald21
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1 Answers1

1

Try declaring result as signed.

reg signed [15:0] result;

(See In verilog printing signed integer value stored in a variable of type reg)

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wilcroft
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