0

I am trying to write a top verilog with instansiations of a few identical modules. the first instansiation should be connected outside, while the other instansiations should be floating. Can anyone help me use the AUTO's with AUTO_TEMPLATE to have emacs connect all inputs to zero, and leave all outputs empty []. I don't have any identification in the module IO name indicating if its input or output (so I can't use wildcards) Is there a way that the tool can identify all inputs (and connect to zero) and all outputs (and leave floating) by itself? Thanks

tom
  • 31
  • 6
  • Could you please edit your question to include an example? – ChrisGPT was on strike Jul 02 '15 at 15:44
  • 1
    I'm assuming you are using [verilog-mode](http://www.veripool.org/wiki/verilog-mode). You might want to use AUTOTIEOFF and/or AUTOUNUSED, see slide 19 [here](http://www.veripool.org/papers/verilog-mode_veritedium_20090925.pdf) – Greg Jul 02 '15 at 17:10

1 Answers1

1

I'v managed to have such modules instantiated by using the auto_template with lisp:

/* module_name AUTO_TEMPLATE ( .(.*) (@"(if (equal vl-dir \"output\") \"\" (concat vl-width \"'b0\"))"), );

*/ that way - all inputs are 0, and outputs are left unconnected!!

tom
  • 31
  • 6