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This is closely related to Remove item from a Makefile variable?.

The answer tells us to use filter-out, but it returns in in a new variable. I need it to modify the existing variable.

The issue I am facing is a GNUmakefile that does the following:

SRCS = $(wildcard *.cpp)
ifeq ($(SRCS),)             # workaround wildcard function bug in GNU Make 3.77
SRCS = $(shell echo *.cpp)
endif

OBJS = $(SRCS:.cpp=.o)

SRCS ends up with a few *.cpp files it does not need, like one that is used in a Borland Developer Studio project.

How do we filter in-place without using a new variable?

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  • Does using adding `SRCS := $(filter-out bad.cpp,$(SRCS))` between the `endif` and `OBJS` assignment line work for what you want here? – Etan Reisner Jul 01 '15 at 04:13
  • Etan's got the right answer. But, really? Backward compat for GNU make 3.77... 17 years old now? Does anyone really still use 3.77 anywhere? – MadScientist Jul 01 '15 at 20:12
  • @MadScientist - This particular library was written in the 1990s. It still supports a lot of older gear, like OpenBSD's GCC 4.2.1. Its got all kinds of goodness baked in :) – jww Jul 01 '15 at 20:15

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