3

Resource

program main(); 
int a; 

initial 
begin 
#10 a = 10; 
#10 a = 20; 
#10 a = 30; 
#10 $finish; 
end 

task pass_by_val(int i); 
forever 
@i $display("pass_by_val: I is %0d",i); 
endtask 


task pass_by_ref(ref int i); 
forever 
@i $display("pass_by_ref: I is %0d",i); 
endtask 

initial 
pass_by_val(a); 

initial 
pass_by_ref(a);

I am refering above site and run but I have some error message like this.

Reference argument is illegal inside static task function declaration.

Chamath
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bunch
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1 Answers1

4

Generally tasks/functions inside module/programs are static by default, As per Section 13.5.2 Pass by reference of IEEE 1800 - 2012

It shall be illegal to use argument passing by reference for subroutines with a lifetime of static.

To resolve only use pass by referece 'ref' to an automatic task/function

task automatic pass_by_ref(ref int i); 
forever 
@i $display("pass_by_ref: I is %0d",i); 
endtask
Emman
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  • As I mentioned in my other [post](http://stackoverflow.com/questions/31017629/what-does-ref-mean-in-systemverilog) to you, pass by reference has many more restrictions pass by value. The arguments of static tasks and functions are static variables that can be accessed from outside the routine. If the routine was not currently active, the argument variables would be referencing invalid data. – dave_59 Jun 24 '15 at 14:33