STM32 documentation says that the I-CODE and D-CODE buses are connected to the internal flash memory. The I-CODE bus is used to fetch instructions and the D-CODE bus is used for data access in the code memory region (literal load).
The question is why two separate buses are used? Can they provide simultaneous and absolutely independent access to flash memory?
As you can see from the stm32 RM0090 Reference manual (page 73), I-CODE and D-CODE busses cannot access the flash memory independently, they do however access the flash interface independently:
As to why there are two: they have separate chaches, also the I-CODE bus implements prefetch, which would be useless for data fetching. Relevant part of the reference manual (page 84):
Data management
Literal pools are fetched from Flash memory through the D-Code bus during the execution stage of the CPU pipeline. The CPU pipeline is consequently stalled until the requested literal pool is provided. To limit the time lost due to literal pools, accesses through the AHB databus D-Code have priority over accesses through the AHB instruction bus I-Code. If some literal pools are frequently used, the data cache memory can be enabled by setting the data cache enable (DCEN) bit in the FLASH_ACR register. This feature works like the instruction cache memory, but the retained data size is limited to 8 rows of 128 bits.
