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I have this CPU.hdl code.

CHIP CPU {

IN  inM[16],         // M value input  (M = contents of RAM[A])
    instruction[16], // Instruction for execution
    reset;           // Signals whether to re-start the current
                     // program (reset=1) or continue executing
                     // the current program (reset=0).

OUT outM[16],        // M value output
    writeM,          // Write into M? 
    addressM[15],    // Address in data memory (of M)
    pc[15];          // address of next instruction

PARTS:
Not(in=instruction[15], out=isAcmd);
Not(in=isAcmd, out=isCcmd);

// Create the ALU chip.
// First input to ALU is always D; 2nd is A or M based on inst[12]
Mux16(a=outA, b=inM, out=outAM, sel=instruction[12]);
ALU(x=outD, y=outAM, zx=instruction[11], nx=instruction[10], zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6], out=outM, out=outALU, out=inD, zr=zr, ng=ng);
//also need logic as to whether to write to M ... it's part of the instruction
And(a=isCcmd, b=instruction[3], out=writeM);
 .
 .
 .
}

I am trying to understand the CPU.hdl. I don't understand the 2 lines after the PARTS. What do they accomplish?

Lundin
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theOtherOne
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2 Answers2

0

PARTS instantiates new components inside you CPU.

For example. there is a NOT component, where the port named in is connected to signal instruction[15]

Philippe
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0

From the book:

In order to figure out what this 16-bit word means, if can be broken into the fields "i xx a cccccc ddd jjj". The i-bit codes the instruction type, which is 0 for an A-instruction, and 1 for a C-instruction.

The two lines in question are splitting instruction[15] into 2 pins. Maybe splitting them with a DMux might make more sense to you:

DMux(in=true, sel=instruction[15], a=aInstruction, b=cInstruction);

Draw the truth table for both ways, and it should make sense to ya.

Salar
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