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I am doing a project in college and want to produce a triangular wave using a DAC2904 and a Spartan 3 xc3s5000 board.

I have written code for it but is not working.

I don't know may be it is the problem in code or in my ucf file:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;   

entity traingular is
    Port ( 
        clk :     in  std_logic; -- on board clock           
        reset :   in  std_logic;
        dac_clk : out std_logic; -- clk for dac module           
        output :  out std_logic_vector(13 downto 0); -- output to dac   
        wr_dac :  out std_logic    -- pulse given to write pin  of dac ic.
    );
end traingular;

architecture Behavioral of traingular is
    signal counter :   unsigned(3 downto 0);
    signal divide :    std_logic_vector(15 downto 0);
    signal sampling_clk , clk_s  : std_logic;
    signal decade :    std_logic_vector(3 downto 0);

-- decade counter used because on board clk freq is 40 hz
-- so the code written below reduce the freq which is applied to dac module very much

begin
    process(clk, reset)
    begin
        if (reset = '1' ) then
            decade <= (others => '0');
        elsif (clk' event and clk = '1') then
            if (decade = "1010") then 
                decade <= (others => '0');
            else 
                decade <= std_logic_vector(unsigned(decade) + 1);
            end if;
        end if; 
    end process;

    clk_s <= '1' when decade = "1010" else
             '0';

    process(clk_s , reset)
    begin
        if (reset='1') then
            divide <= (others => '0');
        elsif (clk_s'event and clk_s = '1') then
            divide <= std_logic_vector(unsigned(divide) + 1);
        end if;
    end process;          

    sampling_clk <= divide(2);

-- input click is still fast so clock is divided further

    dac_clk <= sampling_clk;

    wr_dac <= sampling_clk;

    process(clk , reset)
    begin

-- code below is for counter which will further feed to dac to produce traingular wave.
        if (reset = '1' ) then
            counter <= (others => '0');
        elsif (clk' event and clk = '1') then
            if (counter = "1010") then 
                counter <= (others => '0');
            else 
                counter <= counter + 1;
            end if;
        end if; 
    end process;

    output <= "0000000000" & std_logic_vector(counter); -- output to dac.

end Behavioral;

So, can you guys tell me what is the problem in my code.

siddu
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    Can you add some specificity? Can you tell us what it's supposed to do, what rate the dac clock and write pulse are supposed to occur at? Is there a reference for the DAC? I don't believe your board has a 40hz clock. How do we replicate the problem? There is no testbench. –  May 28 '15 at 10:02
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    It's amplitude is designed to be so small (under 1 mv pk-pk), how can you possibly tell whether it's working or not? –  May 28 '15 at 10:29
  • sorry clock of board is 40 Mhz .and as i am realizing the output on cro so i can tell you it is not working – siddu May 28 '15 at 10:56
  • Please provide simulation testbench or waveforms. – Jonathan Drolet May 28 '15 at 14:13
  • Did it work correctly in simulation? –  May 28 '15 at 18:19
  • The series of comments mentioning testbench, waveforms and simulation are clues. We debug VHDL programs in simulations. I wrote a testbench, simulated your design, found the datasheet link and still don't have a clue what frequency your triangular waveform is supposed to have and can't tell the intended frequency of `dac_clk` and see `wr_dac` as promiscuously wide (covering multiple values of output). Your question doesn't provide a [Minimal, Complete, and Verifiable example](http://stackoverflow.com/help/mcve). –  May 29 '15 at 00:54

1 Answers1

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_signed.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tri_wave is
    Port ( clk : in  STD_LOGIC;
           rst :in  STD_LOGIC;
           up_step_size,down_step_size:in std_logic_vector(2 downto 0);
           dac_out : out  STD_LOGIC_VECTOR (7 downto 0));
end tri_wave;

architecture Behavioral of tri_wave is
signal dac_wav:std_logic_vector(7 downto 0);
signal count:std_logic_vector(7 downto 0);
signal dir:std_logic:='0';
begin
process(clk,rst,dir)
    begin
        if rst='1' then
            count<=(others=>'0');
        elsif dir='0' then
            if clk'event and clk='1' then
                if count="01111111" then
                    dir<='1' ;
                else
                    count<= count + up_step_size;
                end if;
            end if;
        elsif dir='1' then 
                if clk'event and clk='1' then
                    if count="10000000" then
                        dir<='0' ;
                    else
                        count<= count - down_step_size;
                    end if;
            end if;
        end if;
    end process;
--dac_out<=count;
dac_out<=count(count'high) & count(6 downto 0);
end Behavioral;

i think this code gives u better idea just creaet tb and simulae i odelsim u will get it.
user7395823
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    While this code may answer the question, providing additional context regarding why and/or how this code answers the question improves its long-term value. – Donald Duck Jan 09 '17 at 18:20