In NVIDIA Fermi and Kepler GPUs (probably Maxwell too), an L1 cache line is 128-bytes long, while an L2 cache line is 32-byte long. Shouldn't that be the other way around? I mean, L1 is much smaller, shouldn't it try to cache shorter segments of memory to prevent thrashing?
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artless noise
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Memory transactions are nominally warp wise, and warps contain 32 threads. A 128 byte L1 cache line corresponds to each thread in a warp reading a 32 bit word (the standard transaction size). Makes sense to me..... – talonmies May 25 '15 at 11:17