VHDL DMUX with Generics (1:8 DMUX)

Question

I wrote this entity but i don't know how to write the architecture.It has to be done by using generics and it needs to work for any DMUX (1:2,1:4,1:8,1:16 etc) if I change the Nr_sel (number of selection inputs). The data(input) is on 1 bit.

entity DMUX is
generic (
    Nr_sel: integer:= 3
);
port (
    Input: in std_logic;
    Sel: in std_logic_vector (Nr_sel - 1 downto 0);
    Outputs: out std_logic_vector(2**Nr_sel - 1 downto 0)
);  
end DMUX;

Try the search function before asking. This appears to have been asked before. See [Use a generic to determine (de)mux size in VHDL?](http://stackoverflow.com/questions/5891700/use-a-generic-to-determine-demux-size-in-vhdl) — , May 22 '15 at 18:41

FRob · Answer 1 · 2015-05-22T22:10:37.947

1

It could be achieved the following way:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity DMUX is
    Generic (
        num_sel : positive := 1 -- or 2, 3, ... etc.
    );
    Port (
        SEL  : in   unsigned(num_sel - 1 downto 0);
        DIN  : in   std_logic;
        DOUT : out  std_logic_vector(2**num_sel - 1 downto 0)
    );
end entity DMUX;

architecture Behavioral of DMUX is
begin

output_p : process (
    SEL,
    DIN
    )
begin

    -- default assignment
    DOUT <= (others => '0');
    DOUT(to_integer(SEL)) <= DIN;

end process output_p;

end architecture Behavioral;

Depending on your needs, you could also have low-active logic, i.e. all ones (others => '1') and invert DIN.

edited May 22 '15 at 22:10

answered May 22 '15 at 16:46

FRob

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This isn't valid VHDL. See IEEE Std 1076-2008, 11.3 Process Statement, the BNF, re: your line 29 the reserved work `process` is required, as in `end process output_p;` where `output_p` is the process label. – May 22 '15 at 19:04
Aren't there two drivers for the same signal? – Eugene Sh. May 22 '15 at 21:58
@DavidKoontz I typed this in notepad... Why didn't you go ahead and edit it when you noticed? – FRob May 22 '15 at 22:04
@EugeneSh. No, there is one driver for DOUT. You get one driver per prices according to the longest prefix rule. – FRob May 22 '15 at 22:06
But `DOUT(to_integer(SEL))` is assigned with 0 and with `DIN`, isn't it? – Eugene Sh. May 22 '15 at 22:11
@EugeneSh. But it's a sequential statement inside a process, so demultiplexing logic to resolve this will be generated. Prices was supposed to be process above. – FRob May 22 '15 at 22:13
@EugeneSh. In a process, only the last assignment to a signal is effective (until end process or wait statement), so FRob's logic is correct and only a single driver per bit is generated. Note that this is not the case for variables. – Jonathan Drolet May 22 '15 at 22:35

score 0 · Answer 2 · answered May 22 '15 at 22:02

I believe the right method would be to use generate, since we have a variable number of outputs, while all of them have to be assigned, and without any sequential logic:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;

entity DMUX is
generic (
    Nr_sel: integer:= 3
);
port (
    Input: in std_logic;
    Sel: in std_logic_vector (Nr_sel - 1 downto 0);
    Outputs: out std_logic_vector(2**Nr_sel - 1 downto 0)
);  
end DMUX;

architecture Arch of DMUX is
begin
    GEN_OUT:
    for i in 0 to (2**Nr_sel - 1) generate
        Outputs(i) <= Input when (to_integer(Sel) = i) else '0';
    end generate GEN_OUT;
end Arch;

I haven't tested it's functionality, but it compiles and gives the idea.

VHDL DMUX with Generics (1:8 DMUX)

2 Answers2