I'm compiling C++ code for Webots (a robotic simulator), by means of makefiles, and I'm using the generic makefile Makefile.include
Webots supplies to ease the process.
I build by own makefile, set a bunch of required variables and then call that makefile that sets all the necessary rules for compilation. That's how it was supposed to work anyway.
I'm getting the following error:
make[1]: *** No rule to make target 'USER_PREBUILD'. Stop.
/usr/share/webots/resources/Makefile.include:503: recipe for target 'pre-build' failed
make: *** [pre-build] Error 2
And looking at the relevant line (from Makefile.include
):
$(SUPPORTED_TARGETS): post-build
USER_PREBUILD:
USER_POSTBUILD:
pre-build:
@$(MAKE) --silent USER_PREBUILD
post-build: main-build
@$(MAKE) --silent USER_POSTBUILD
$(TARGETS): pre-build
main-build: $(TARGETS)
I'm not sure if there is not a syntax error when calling make
in the pre-build
and post-build
, or if USER_PREBUILD
and USER_POSTBUILD
are supposed to be concrete files, but even if replace them with $(USER_PREBUILD)
I get *** No targets specified and no makefile found
.
So I assume I would need to set those variables before calling the external makefile, but what exactly is the syntax if I don't have anything to be done before building?
Strangely, even despite these errors, the program compiles (I get the *.o, *.d and the binary on the build
folder), but it never copies the binary to the destination folder.