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Following truth table resulted from the circuit below. SR(NOR) latch is used. I have tried several times to trace through the circuit to see how truth table values are produced but its not working. Can someone explain to me what is going on ? This circuit was introduced in conjunction with racing although I am not sure if it has anything to do with it.

NOTE: "CLOCK" appears as a straight line to show how its connected everything. It is a normal clock that oscillates between 1 and 0. (this is how my instructor drew it). enter image description here

enter image description here

Jenna Maiz
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  • you should post this question in [electrical engineering](http://electronics.stackexchange.com/) – dlavila May 10 '15 at 03:42
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    I'm voting to close this question as off-topic because it belongs on [electronics.se] –  May 10 '15 at 03:43
  • I am looking at the related questions...and there is a ton of same type(circuits/logic) questions with plenty of upvotes. What is different about my question ? – Jenna Maiz May 10 '15 at 03:44
  • I'm voting to close this question as off-topic because it is about circuits and signal processing, not programming. – Pang May 12 '15 at 01:37
  • @Pang Might as well vote the entire set of "related" questions off-topic as they deal with circuits and signal processing. Honestly, I asked the same question on Electrical Engineering website but its this website that yielded an appropriate answer... – Jenna Maiz May 12 '15 at 04:21

1 Answers1

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Strictly, this does belong on EE. The other questions you've found are likely to be old - before EE was established.

You should look at the 1-to-0 transitions of the clock. When that occurs and only when that occurs, the value currently on S is transferred to Q.

The Race condition appears when the clock signal is delayed, even with the tiny amount of copper track between real components. The actual waveform is not 1-0 or 0-1, it ramps between the two values. A tiny variation between two components, one seeing the transition at say 2.7V and the other at 2.5 would mean that the first component moves the value from S to Q fractionally before the second, so when the second component decides to transfer the value, it may see the value after the transfer has occurred on the prior component. You therefore may have a race between the two. These delays can also be affected by supply-rail stability and temperature, so the whole arrangement can become unreliable if not carefully designed. The condition is often overcome be deliberately routing the clock so that it will arrive at the last component in the chain first, giving that end of the chain a head-start.

I've worked on systems where replacing a component with a faster version caused the circuit to stop working. The new component was working too fast for the remainder of the circuit - and you needed to deliberately select (or use factory-selected) slower versions.

On a related note, before hard-drives became cheap, and floppy-drives (you may need to google that) before them it was common to use casste tapes (even more likely you'd need google on those.) Cheap and cheerful was best. If you used a professional quality recorder/player, you'd often get unusable results.

Magoo
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  • Could you clarify a little bit how to look at only the 1-to-0 transition ? In terms of the truth table, how would I do this ? I am not given a waveform diagram for the circuit. – Jenna Maiz May 10 '15 at 05:14
  • As you progress down the table you've presented, each line shows the result after the clock has changed. If the clock was 0 and is now 1, the succeeding line shows the Q outputs unchanged. They only change when the clock was a 1 and is now a 0 ("negative edge trigger") So - changing the clock from 1 to 0 moves the S-input value to Q-output. The race occurs if the previous stage has transferred its contents before the next reacts to the tigger due to delays as outlined. – Magoo May 10 '15 at 06:02
  • I think I understand the truth table now. But if you were given just the circuit(w/o truth table) would you know that the circuit is negative edge triggered ? – Jenna Maiz May 10 '15 at 14:25
  • No. It's a characteristic of the particular component in question. Negative-edge triggering is conventional, but I believe that positive-edge triggered are available. A negative-edge trigger device can e turned into a positive-edge using an inverter gate on the clock terminal of course. Sometimes on the circuit a symbol resembling the (negative-going) edge of ithe clock signal s shown on the clock pin. – Magoo May 10 '15 at 17:01